zl30136 Zarlink Semiconductor, zl30136 Datasheet

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zl30136

Manufacturer Part Number
zl30136
Description
Gbe And Telecom Rate Network Interface Synchronizer
Manufacturer
Zarlink Semiconductor
Datasheet

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Features
Provides synchronous clocks for network interface
cards that support synchronous Ethernet (SyncE)
in addition to telecom interfaces (T1/E1, DS3/E3,
etc.)
Supports the requirements of ITU-T G.8262 for
Synchronous Ethernet equipment slave clocks
(EEC option 1 and 2)
Synchronizes to telecom reference clocks (2 kHz,
N*8 kHz up to 77.76 MHz) or to Ethernet reference
clocks (25 MHz, 50 MHz, 62.5 MHz, 125 MHz, and
155.52 MHz)
Generates Ethernet clocks (12.5 MHz, 25 MHz,
50 MHz, 62.5 MHz, or 125 MHz)
Programmable telecom synthesizer generates
clock frequencies of any multiple of 8 kHz up to
100 MHz
Selectable loop bandwidth of 14 Hz, 28 Hz, 890 Hz,
or 0.1 Hz
Generates several styles of output frame pulses
with selectable pulse width, polarity and frequency
Provides 3 sync inputs for output frame pulse
alignment
Flexible input reference monitoring automatically
disqualifies references based on frequency and
phase irregularities
sync0
sync1
sync2
ref0
ref1
ref2
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
/N1
/N2
Copyright 2008, Zarlink Semiconductor Inc. All Rights Reserved.
mode
Figure 1 - Functional Block Diagram
lock
Zarlink Semiconductor Inc.
osci
hold
sync
ref
DPLL
1
Applications
osco
Supports automatic hitless reference switching
and short term holdover during loss of reference
inputs
DPLL can be configured to provide synchronous or
asynchronous clock outputs
Configurable through a serial interface (SPI or I
Supports IEEE 1149.1 JTAG Boundary Scan
GbE network interface cards that support
synchronous Ethernet (SyncE)
GPON ONT/ONU
T1/E1 line cards
DS3/E3 line cards
ZL30136GGG
ZL30136GGG2 64 Pin CABGA*
I
2
Network Interface Synchronizer
C/SPI
Programmable
Synthesizer
Ethernet
N*8kHz
APLL
*Pb Free Tin/Silver/Copper
Ordering Information
JTAG
-40°C to +85°C
GbE and Telecom Rate
64 Pin CABGA
Short Form Data Sheet
eth_clk
p_clk
p_fp
ZL30136
September 2008
Trays
Trays
2
C)

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zl30136 Summary of contents

Page 1

... Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2008, Zarlink Semiconductor Inc. All Rights Reserved. Network Interface Synchronizer Ordering Information ZL30136GGG ZL30136GGG2 64 Pin CABGA* *Pb Free Tin/Silver/Copper • Supports automatic hitless reference switching and short term holdover during loss of reference inputs • ...

Page 2

... Change Summary Changes from February 2008 issue to September 2008 issue. Page Item 1 Ordering Information ZL30136 Change Corrected ordering part number. 2 Zarlink Semiconductor Inc. Data Sheet ...

Page 3

... Serial Interface (SPI sck/scl I/B Clock for Serial Interface (LVCMOS). Serial interface clock. When i2c_en = 0, this pin acts as the sck pin for the serial interface. When i2c_en = 1, this pin acts as the scl pin (bidirectional) for the I ZL30136 Description . dd dd interface. 3 Zarlink Semiconductor Inc ...

Page 4

... H5 osco O Oscillator Master Clock Output (LVCMOS). This pin must be left unconnected when the osci pin is connected to a clock oscillator. ZL30136 Description 2 C interface. C Interface Enable (LVCMOS). If set high, the I 4 Zarlink Semiconductor Inc. ...

Page 5

... Analog Ground. 0 Volts Input I - Input, Internally pulled down Input, Internally pulled Output A - Analog P - Power G - Ground ZL30136 Description nominal. DC nominal. DC nominal. DC nominal Zarlink Semiconductor Inc. Short Form Data Sheet ...

Page 6

... B ref0 mode C sck/ cs_b/ scl asel0 D so sda E lock int_b F AV tms CORE G AV tdi SS H hold i2c_en corner is identified by metallized markings. ZL30136 ref1 sync2 apll_filter NC ref2 filter_ref0 V AV filter_ref1 ...

Page 7

... The ZL30136 synchronizes to backplane clocks and generates a synchronized and jitter attenuated Ethernet clock and a PDH clock. A typical application is shown in Figure 2. In this application, the ZL30136 translates a 19.44 MHz clock from the telecom backplane to an Ethernet clock rate for the GbE PHY and filters the jitter to ensure compliance with related clock standards ...

Page 8

...

Page 9

... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...

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