zl30131 Zarlink Semiconductor, zl30131 Datasheet
zl30131
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zl30131 Summary of contents
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... SDH line cards up to STM-64 ref_out osci Tx DPLL Rx DPLL 2 hold lock I C/SPI JTAG Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. ZL30131 Short Form Data Sheet February 2008 Ordering Information 100 Pin CABGA Trays 100 Pin CABGA* Trays osco diff0_p/n ...
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... MHz. K8 p0_fp0 O Programmable Synthesizer 0 - Output Frame Pulse 0 (LVCMOS). This output can be configured to provide virtually any style of output frame pulse associated with the p0 clocks. The default frequency for this frame pulse output is 8 kHz. ZL30131 Description . dd dd. 5 Zarlink Semiconductor Inc. ...
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... Lock Indicator (LVCMOS). This is the lock indicator pin for the Tx DPLL. This output goes high when the Tx DPLL’s output is frequency and phase locked to the input reference. J1 hold O Holdover Indicator (LVCMOS). This pin goes high when the Tx DPLL enters the holdover mode. ZL30131 Description 6 Zarlink Semiconductor Inc. Short Form Data Sheet ...
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... This pin is internally pulled up to Vdd. If this pin is not used then it should be connected to GND. K3 tck I Test Clock (LVCMOS): Provides the clock to the JTAG test logic. If this pin is not used then it should be pulled down to GND. ZL30131 Description 2 C interface interface (LVCMOS) ...
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... Positive Supply Voltage. +1.8V CORE Positive Analog Supply Voltage. +3. C10 Positive Analog Supply Voltage. +1.8V CORE ZL30131 Description nominal. DC nominal. DC nominal. DC nominal Zarlink Semiconductor Inc. Short Form Data Sheet . If this pin is not used DD ...
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... Analog Ground. 0 Volts Input I - Input, Internally pulled down Input, Internally pulled Output A - Analog P - Power G - Ground ZL30131 Description 9 Zarlink Semiconductor Inc. Short Form Data Sheet ...
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... F si/ asel2 asel1 sdh G so int_b NC H lock AV AV CORE SS J hold i2c_en tms K diff0_en tdi tck corner is identified with a dot. ZL30131 ref7 AV apll_filter ref5 IC filter_ref0 AV CORE ref6 IC filter_ref1 ...
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... Each path is controlled with separate DPLLs (Tx DPLL, Rx DPLL) which are both independently configurable through the serial interface (SPI Figure 2. In this application, the ZL30131 translates the 19.44 MHz clock from the telecom rate backplane (system timing bus), translates the frequency to 622.08 MHz or 156.25 MHz for the PHY Tx clock, and filters the jitter to ensure compliance with the related standards ...
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... Zarlink Semiconductor 2005 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...