zl30146 Zarlink Semiconductor, zl30146 Datasheet

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zl30146

Manufacturer Part Number
zl30146
Description
Synce Sonet/sdh Line Card Pll
Manufacturer
Zarlink Semiconductor
Datasheet

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Features
Synchronizes to standard telecom or Ethernet
backplane clocks and provides jitter filtered output
clocks for SONET/SDH, PDH and Ethernet network
interface cards
Supports the requirements of ITU-T G.8262 for
synchronous Ethernet Equipment slave Clocks
Meets the SONET/SDH jitter generation
requirements up to OC-192/STM-64
Two independent DPLLs provides timing for the
transmit path (backplane to line rate) and the
receive path (recovered line rate to backplane)
Synchronizes to telecom reference clocks (2 kHz,
N*8 kHz up to 77.76 MHz, 155.52 MHz) or to
Ethernet reference clocks (25 MHz, 50 MHz,
62.5 MHz, 125 MHz)
Selectable loop bandwidth of 14 Hz, 28 Hz, 890 Hz,
3.5 Hz, 1.7 Hz, or 0.1 Hz
Supports automatic hitless reference switching and
short term holdover during loss of reference inputs
Generates standard SONET/SDH clock rates (e.g.,
19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz,
622.08 MHz) or Ethernet clock rates (e.g., 25 MHz,
50 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for
synchronizing Ethernet PHYs
sync0
ref0
ref1
ref2
ref3
ref4
osci
Ref/Sync
Monitors
Ports
Input
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
osco
m ode
Copyright 2009, Zarlink Semiconductor Inc. All Rights Reserved.
hold lock
Figure 1 - Functional Block Diagram
ref
ref
m
n
Zarlink Semiconductor Inc.
/sync
n
I2C/SPI
1
Rx DPLL
Tx DPLL
Applications
SyncE SONET/SDH Line Card PLL
Programmable output synthesizer to generate
telecom clock frequencies from any multiple of
8 kHz up to 100 MHz (e.g., T1/E1, DS3/E3)
Generates several styles of output frame pulse
with selectable pulse width, polarity, and frequency
Configurable input to output delay and output to
output phase alignment
Configurable through a serial interface (SPI or I
DPLLs can be configured to provide synchronous
or asynchronous clock outputs
ITU-T G.8262 Line Cards which support 1 GbE
and 10 GbE interfaces
SONET/SDH line cards up to OC-192/STM-64
JTAG
ZL30146GGG
ZL30146GGG2
*Pb Free Tin/Silver/Copper
Ordering Information
-40
Program m able
64 Pin CABGA
64 Pin CABGA*
Synthesizer
Ethernet/
o
SONET
C to +85
APLL
N*8kHz
Short Form Data Sheet
o
C
ZL30146
Trays
Trays
p_clk
p_fp
diff
apll_clk
February 2009
2
C)

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zl30146 Summary of contents

Page 1

... SONET/SDH line cards up to OC-192/STM-64 Rx DPLL ref m ref /sync DPLL I2C/SPI JTAG Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. ZL30146 Short Form Data Sheet February 2009 64 Pin CABGA Trays 64 Pin CABGA* Trays p_clk Program m able ...

Page 2

... Each path is controlled with separate DPLLs (Tx DPLL, Rx DPLL) which are both independently configurable through the serial interface (SPI Figure 2. In this application, the ZL30146 translates the 19.44 MHz clock from the telecom rate backplane (system timing bus), translates the frequency to 622.08 MHz or 156.25 MHz for the PHY Tx clock, and filters the jitter to ensure compliance with the related standards ...

Page 3

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Page 4

... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...

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