zl30142 Zarlink Semiconductor, zl30142 Datasheet

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zl30142

Manufacturer Part Number
zl30142
Description
Synce Sonet/sdh G.8262/stratum 3 System Synchronizer
Manufacturer
Zarlink Semiconductor
Datasheet

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zl30142GGG2
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zl30142GGG2
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Features
Supports the requirements of ITU-T G.8262 for
synchronous Ethernet Equipment slave Clocks
(EEC option 1 and 2)
Supports the requirements of Telcordia GR-1244
Stratum 3 and GR-253, ITU-T G.812, G.813
Supports ITU-T G.823, G.824 and G.8261 for 2048
kbit/s and 1544 kbit/s interfaces
Meets the SONET/SDH jitter generation
requirements up to OC-48/STM-16
Synchronizes to telecom reference clocks (2 kHz,
N*8 kHz up to 77.76 MHz, 155.52 MHz) or to
Ethernet reference clocks (25 MHz, 50 MHz,
62.5 MHz, 125 MHz)
Generates standard SONET/SDH clock rates (e.g.,
19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz,
622.08 MHz) or Ethernet clock rates (e.g., 25 MHz,
50 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for
synchronizing Gigabit Ethernet PHYs
Programmable output synthesizer generates
telecom clock frequencies from any multiple of
8 kHz up to 100 MHz
Generates several styles of telecom frame pulses
with selectable pulse width, polarity and frequency
Internal state machine automatically controls mode
of operation (free-run, locked, holdover)
sync0
sync1
sync2
ref0
ref1
ref2
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
/N1
/N2
Copyright 2009, Zarlink Semiconductor Inc. All Rights Reserved.
mode
Figure 1 - Functional Block Diagram
lock
osci
Zarlink Semiconductor Inc.
hold
sync
ref
DPLL
G.8262/Stratum 3 System Synchronizer
1
osco
Applications
Flexible input reference monitoring automatically
disqualifies references based on frequency and
phase irregularities
Provides automatic reference switching and
holdover during loss of reference input
Supports master/slave configuration and dynamic
input to output delay compensation for
AdvancedTCA
Configurable input to output delay and output to
output phase alignment
ITU-T G.8262 System Timing Cards which support
1 GbE interfaces
Telcordia GR-253 Carrier Grade SONET/SDH
Stratum 3 System Timing Cards
I
ZL30142GGG
ZL30142GGG2
2
C/SPI
Programmable
Synthesizer
Ethernet
SONET/
N*8kHz
APLL
*Pb Free Tin/Silver/Copper
Ordering Information
JTAG
TM
-40
64 Pin CABGA
64 Pin CABGA*
o
C to +85
SyncE SONET/SDH
Short Form Data Sheet
o
C
diff
apll_clk
p_clk
p_fp
ZL30142
Trays
Trays
February 2009

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zl30142 Summary of contents

Page 1

... Ethernet ref APLL DPLL Programmable Synthesizer sync N*8kHz hold lock I 2 C/SPI Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. ZL30142 SyncE SONET/SDH Short Form Data Sheet February 2009 64 Pin CABGA Trays 64 Pin CABGA* Trays diff apll_clk p_clk ...

Page 2

... High Level Overview The ZL30142 SONET/SDH/GbE Stratum 3 System Synchronizer and SETS device is a highly integrated device that provides all of the functionality that is required for a central timing card in carrier grade network equipment. The basic functions of a central timing card include: • Input reference monitoring for both frequency accuracy and phase irregularities • ...

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Page 4

... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...

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