zl30122 Zarlink Semiconductor, zl30122 Datasheet
zl30122
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zl30122 Summary of contents
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... Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2006, Zarlink Semiconductor Inc. All Rights Reserved. Low Jitter Line Card Synchronizer an email to ZL30122GGG ZL30122GGG2 64 Pin CABGA* *Pb Free Tin/Silver/Copper • Provides 3 reference inputs which support clock frequencies with any multiples of 8 kHz up to 77.76 MHz in addition to 2 kHz • ...
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... Applications TM • AMCs for AdvancedTCA and MicroTCA Systems • Multi-Service Edge Switches or Routers • DSLAM Line Cards • WAN Line Cards • RNC/Mobile Switching Center Line Cards • ADM Line Cards ZL30122 2 Zarlink Semiconductor Inc. Data Sheet ...
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... Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 DPLL Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 DPLL Mode Of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3 Ref and Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.4 Ref and Sync Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.5 Output Clocks and Frame Pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.6 Configurable Input-to-Output and Output-to-Output Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.0 Software Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.0 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 ZL30122 Table of Contents 3 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 1 - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Automatic Mode State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 3 - Reference and Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 4 - Output Frame Pulse Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5 - Behaviour of the Guard Soak Timer during CFM or SCM Failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 6 - Output Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7 - Phase Delay Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 ZL30122 List of Figures 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 1 - DPLL Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 2 - Set of Pre-Defined Auto-Detect Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 3 - Set of Pre-Defined Auto-Detect Sync Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 4 - Output Clock and Frame Pulse Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 5 - Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ZL30122 List of Tables 5 Zarlink Semiconductor Inc. Data Sheet ...
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... Differential Output Enable (LVCMOS, Schmitt Trigger). When set high, the u differential LVPECL driver is enabled. When set low, the differential driver is tristated reducing power consumption. This function is also controllable through software registers. This pin is internally pulled up to Vdd. ZL30122 Description ss. 6 Zarlink Semiconductor Inc. ...
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... Oscillator Master Clock Input (LVCMOS). This input accepts a 20 MHz reference from a clock oscillator (XO, XTAL). The stability and accuracy of the clock at this input determines the free-run accuracy and the long term holdover stability of the output clocks. ZL30122 Description 7 Zarlink Semiconductor Inc. ...
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... Analog Ground. 0 Volts Input I - Input, Internally pulled down Input, Internally pulled Output A - Analog P - Power G - Ground ZL30122 Description nominal. DC nominal. DC nominal. DC nominal Zarlink Semiconductor Inc. Data Sheet ...
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... Functional Description The ZL30122 SONET/SDH Line Card Synchronizer is a highly integrated device that provides timing and synchronization for network interface cards. The DPLL is capable of locking to one of three input references and provides a wide variety of synchronized output clocks and frame pulses. 1.1 DPLL Features The Digital Phase-Locked Loop synchronizes to one of the qualified references and provides automatic or manual hitless reference switching and a holdover function when no qualified references are available ...
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... The input references are continuously monitored for frequency accuracy and phase regularity least one of the input references is qualified by the reference monitors, then the DPLL will begin lock acquisition on that input. Given a stable reference input, the ZL30122 will enter in the Normal (locked) mode. Normal (locked) ...
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... DPLL will align the output frame pulses to the output clock edge that is diff_clk/sdh_clk/p_clk aligned to the input frame pulse. ZL30122 ref2:0 DPLL sync2:0 Figure 3 - Reference and Sync Inputs input is selected with its corresponding ref n ref n ...
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... Single Cycle Monitor (SCM) The SCM block measures the period of each reference clock cycle to detect phase irregularities or a missing clock edge. In general, if the measured period deviates by more than 50% from the nominal period, then an SCM failure (scm_fail) is declared. ZL30122 2 kHz 8 kHz 64 kHz 1 ...
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... Figure 5 - Behaviour of the Guard Soak Timer during CFM or SCM Failures Sync Ratio Monitor All sync inputs (sync0 to sync2) are continuously monitored to ensure that there is a correct number of reference clock cycles within the frame pulse period. ZL30122 CFM or SCM failures ...
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... Output Clocks and Frame Pulses The ZL30122 offers a wide variety of outputs including one low-jitter differential LVPECL clock (diff_clk_p/n), one SONET/SDH LVCMOS (sdh_clk) output clock and one programmable LVCMOS (p_clk) output clock. In addition to the clock outputs, one LVCMOS SONET/SDH frame pulse output (sdh_fp) and one LVCMOS programmable frame pulse (p_fp) is also available ...
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... Configurable Input-to-Output and Output-to-Output Delays The ZL30122 allows programmable static delay compensation for controlling input-to-output and output-to-output delays of its clocks and frame pulses. Both the SONET/SDH APLL and the Programmable Synthesizer can be configured to lead or lag the selected input reference clock using the DPLL Fine Delay ...
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... Software Configuration The ZL30122 is mainly controlled by accessing software registers through the serial peripheral interface (SPI). The device can be configured to operate in a highly automated manner which minimizes its interaction with the system’s processor can operate in a manual mode where the system processor controls most of the operation of the device ...
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... Reserved 27 Reserved ZL30122 Reset Value (Hex) EE Sync0 and sync1 auto-detected frequency value and sync failure status register 0E Sync2 auto-detected frequency value and sync valid status register 33 Control register for the ref0 and ref1 out of range limit ...
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... Reserved 4F 50 sdh_enable 51 sdh_run 52 sdh_clk_div 53 sdh_clk_offset90 ZL30122 Reset Value (Hex) 04 DPLL lock and holdover status register 03 Leave as default Leave as default 8F Control register to enable the p_clk and p_fp outputs of the programmable synthesizer 0F Control register to generate p_clk, p_fp 00 Control register for the [7:0] bits of the N of ...
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... Reserved 67 custA_mult_0 68 custA_mult_1 69 custA_scm_low 6A custA_scm_high 6B custA_cfm_low_0 ZL30122 Reset Value (Hex) Leave as default 00 Control register for the output/output phase alignrment fine tuning for sdh path 05 Control register to select the sdh_fp frame pulse frequency 23 Control register to select sdh_fp type 00 Bits [7:0] of the programmable frame pulse phase offset in multiples of 1/311 ...
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... ZL30122 Reset Value (Hex) 00 Control register for the custom configuration A: The [15:0] bits of the single cycle CFM low limit 00 Control register for the custom configuration A: The [7:0] bits of the single cycle CFM high limit 00 Control register for the custom configuration ...
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... Addr Register (Hex) Name 7B - Reserved 7F 3.0 References AdvancedTCA, ATCA and the AdvancedTCA and ATCA logos are trademarks of the PCI Industrial Computer Manufacturers Group. ZL30122 Reset Value (Hex) Table 5 - Register Map (continued) 21 Zarlink Semiconductor Inc. Data Sheet Description Type ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...