zl30407qcc Zarlink Semiconductor, zl30407qcc Datasheet

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zl30407qcc

Manufacturer Part Number
zl30407qcc
Description
Sonet/sdh Network Element Pll
Manufacturer
Zarlink Semiconductor
Datasheet
Features
SECOR
PRIOR
Meets requirements of GR-253 for SONET
Stratum 3 and SONET Minimum Clocks (SMC)
Meets requirements of GR-1244 for Stratum 3
Meets requirements of G.813 Option 1 and 2 for
SDH Equipment Clocks (SEC)
Generates clocks for ST-BUS, DS1, DS2, DS3,
OC-3, E1, E3, STM-1 and 19.44 MHz
Holdover accuracy of 4x10
Stratum 3E and ITU-T G.812 requirements
Continuously monitors both references for
frequency accuracy exceeding ±12 ppm
Provides “hit-less” reference switching
Compensates for Master Clock Oscillator
accuracy
Automatically detects frequency of both reference
clocks and synchronizes to any combination of
8 kHz, 1.544 MHz, 2.048 MHz and 19.44 MHz
reference frequencies
Allows Hardware or Microprocessor control
Pin compatible with ZL30410, ZL30402 and
MT90401
RefSel
SEC
RESET
PRI
HW
CS
Acquisition
Secondary
Acquisition
VDD GND
Primary
PLL
PLL
DS
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
R/W
Microport
A0-A6
Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved.
-12
D0-D7
meets GR-1244
Master Clock
Calibration
Frequency
Figure 1 - Functional Block Diagram
MUX
C20i
Zarlink Semiconductor Inc.
MS1 MS2
1
Control State Machine
Core PLL
Applications
Description
The ZL30407 is a Network Element Phase-Locked
Loop designed to synchronize SDH and SONET
systems. In addition, it generates multiple clocks for
legacy PDH equipment and provides timing for ST-
BUS and GCI backplanes.
SONET/SDH Network Element PLL
Synchronization for SDH and SONET Network
Elements
Clock generation for ST-BUS and GCI backplanes
ZL30407QCC
ZL30407QCG1
RefAlign
FCS
LOCK
Ordering Information
HOLDOVER
*Pb Free Matte Tin
80 Pin LQFP Trays
80 Pin LQFP* Trays, Bake & Drypack
Synthesizer
-40qC to +85qC
APLL
Clock
1149.1a
JTAG
IEEE
OE
E3/DS3
E3DS3/OC3
Data Sheet
C155P/N
C34/C44
C19o
C16o
C8o
C6o
C4o
C2o
C1.5o
F16o
F8o
F0o
Tclk
Tdi
Tdo
Tms
ZL30407
Trst
November 2006
R1-17

Related parts for zl30407qcc

zl30407qcc Summary of contents

Page 1

... D0- R/W Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved. SONET/SDH Network Element PLL ZL30407QCC ZL30407QCG1 Applications • Synchronization for SDH and SONET Network Elements • Clock generation for ST-BUS and GCI backplanes ...

Page 2

... The filtering characteristics of the PLL are hardware or software selectable and they do not require any external adjustable components. The ZL30407 uses an external 20 MHz Master Clock Oscillator to provide a stable timing source for the HOLDOVER operation. The ZL30407 operates from a single 3.3 V power supply and offers tolerant microprocessor interface. ZL30407 2 Zarlink Semiconductor Inc. Data Sheet ...

Page 3

... Single 8 kHz Reference Operation: NORMAL --> AUTO HOLDOVER--> HOLDOVER --> NORMAL 36 5.1.4 Dual Reference Operation: NORMAL --> AUTO HOLDOVER--> HOLDOVER --> NORMAL 5.2 Master/Slave Timing Protection Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.3 Programming Master Clock Oscillator Frequency Calibration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.4 Power supply filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.0 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.2 Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 ZL30407 Table of Contents 3 Zarlink Semiconductor Inc. Data Sheet ...

Page 4

... Figure 18 - ST-BUS and GCI Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 19 - DS1 and DS2 Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 20 - C155o and C19o Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 21 - Input Reference to Output Clock Phase Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 22 - Input Control Signal Setup and Hold Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure and DS3 Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 ZL30407 List of Figures 4 Zarlink Semiconductor Inc. Data Sheet ...

Page 5

... Table 18 - Secondary Acquisition PLL Status Register ( Table 19 - Master Clock Frequency Calibration Register 4 (R/ Table 20 - Master Clock Frequency Calibration Register 3 (R/ Table 21 - Master Clock Frequency Calibration Register 2 (R/ Table 22 - Master Clock Frequency Calibration Register 1 (R/ ZL30407 List of Tables 5 Zarlink Semiconductor Inc. Data Sheet ...

Page 6

... Change Updated Ordering Information ZL30407 Zarlink Semiconductor Inc. Data Sheet Tdi Trst 36 Tclk Tms 34 Tdo NC 32 GND C155P 30 C155N VDD 28 AVDD GND 26 IC GND 24 PRI ...

Page 7

... Mode Select 2 (Input). The MS2 and MS1 pins select the ZL30407 mode of operation (Normal, Holdover or Free-run), see Table 2 on page 22 for details. The logic level at this input is sampled by the rising edge of the F8o frame pulse. Connect to ground in Software Control. 7 Zarlink Semiconductor Inc. Data Sheet ...

Page 8

... In the disabled state the LVDS outputs are internally terminated with an integrated 100: resistor (two 50: resistors connected in series). The middle point of these resistors is internally biased from a 1.25 V LVDS bias source. Ground No internal bonding Connection. Leave unconnected. 8 Zarlink Semiconductor Inc. Data Sheet ...

Page 9

... Reference Alignment (Input). In Hardware Control pulling this pin low for 250 Ps initiates phase realignment between the input reference and the generated output clocks. This pin should never be tied low permanently. Please see Section 3.2.5, Reference Alignment (RefAlign) for more information. Internally this pin is pulled down to GND. 9 Zarlink Semiconductor Inc. Data Sheet ...

Page 10

... Chip Select (5 V tolerant input). This active low input enables the microprocessor interface. When CS is set to high, the microprocessor interface is idle and all Data Bus I/O pins will high impedance state. 10 Zarlink Semiconductor Inc. Data Sheet ...

Page 11

... ZL30407. When low, the parallel processor is writing data to the ZL30407. Address tolerant input). Address input for the microprocessor interface the least significant input. Internal Connection (Input). Connect this pin to ground. 11 Zarlink Semiconductor Inc. Data Sheet ...

Page 12

... In Holdover mode, the Core PLL generates a clock based on data collected from past reference signals. The Core PLL enters Holdover mode if the attached Acquisition PLL switches into the Holdover state or under external software or hardware control. ZL30407 12 Zarlink Semiconductor Inc. Data Sheet ...

Page 13

... Meets requirements of G.813 Option 1 for SDH Equipment Clocks (SEC) and GR-1244 for Stratum 4 and Stratum 4E clocks. The maximum phase slope is limited 1.326 ms. ZL30407 FSM Phase Filters Detector FCS FCS2 (Control bit only) Conformance Table 1 - Loop Filter Selection 13 Zarlink Semiconductor Inc. Data Sheet DCO ...

Page 14

... After initiating a reference realignment the PLL will enter Holdover mode for 200ns while aligning the internal clocks to remove the static phase error. The PLL will then begin the normal locking procedure. The LOCK pin will go low 5 sec after the reference realignment is initiated and will remain low for 10 sec. ZL30407 14 Zarlink Semiconductor Inc. Data Sheet ...

Page 15

... After initiating a reference realignment the PLL will enter Holdover mode for 200ns while aligning the internal clocks to remove the static phase error. The PLL will then begin the normal locking procedure. The LOCK pin will go low 5 sec after the reference realignment is initiated and will remain low for 10 sec. ZL30407 15 Zarlink Semiconductor Inc. Data Sheet ...

Page 16

... When the E3DS3/OC3 pin is high then the C155o (155.52 MHz) clock is disabled and the C34/44 clock is output at its nominal frequency. The logic level on the E3/DS3 input determines if the output clock on the C34/44 output is 34.368 MHz (E3) or 44.736 MHz (DS3) (see Figure 4, “C34/C44, C155o Clock Generation Options,” on page 17 for details). ZL30407 16 Zarlink Semiconductor Inc. Data Sheet ...

Page 17

... Normal and Holdover. These three states are complemented by two additional states: Reset and Auto Holdover, which are critical to the ZL30407 operation under changing external conditions. ZL30407 C34/44 Output E3DS3/OC3 0 1 11.184 44.736 8.592 34.368 17 Zarlink Semiconductor Inc. Data Sheet C155 Output E3DS3/OC3 0 1 155.52 disabled active ...

Page 18

... HOLD- OVER RefSel Change 01 OR MS2,MS1 = 01 STATE MS2,MS1 -12 by setting the offset frequency in the Master Clock Frequency 18 Zarlink Semiconductor Inc. Data Sheet Ref: FAIL-->OK AND MS2,MS1 = 00 AND AHRD = 1 AND MHR = 1 {MANUAL} OR Ref: FAIL-->OK AND MS2,MS1 = 00 AND AHRD = 0 {AUTO} {AUTO} AUTO ...

Page 19

... Figure 6 - ZL30407 State Machine in Hardware Control configuration ZL30407 -12 RefSel change NORMAL 00 Ref: OK AND Ref: OK-->FAIL AND MS2,MS1 = 00 MS2,MS1 = 00 {AUTO} HOLD- OVER RefSel Change 01 OR MS2,MS1 = 01 19 Zarlink Semiconductor Inc. Data Sheet (see table Performance Characteristics* on Ref: FAIL-->OK AND MS2,MS1 = 00 AND {AUTO} {AUTO} AUTO HOLD- OVER -9 . ...

Page 20

... A rate of frequency change below 2.9 ppm/sec is suggested. All memory in the ZL30407 is volatile; so any settings of the Master Clock Calibration Register need to be reloaded after each RESET. ZL30407 ) where 000 000 Hz offset offset m 20 Zarlink Semiconductor Inc. Data Sheet ...

Page 21

... Test Access Port (TAP), TAP Controller, Instruction Register (IR) and Test Data Registers (TDR) and all these elements are implemented on the ZL30407. Zarlink Semiconductor provides a Boundary Scan Description Language (BSDL) file that contains all the information required for a JTAG test system to access the ZL30407's boundary scan circuitry. The file is available for download from the Zarlink Semiconductor web site: www ...

Page 22

... Processor Interface Mode of Operation Normal mode Holdover mode Free-run Reserved Table 2 - Operating Modes and States 22 Zarlink Semiconductor Inc. Data Sheet Software Control MS2 MS1 C FCS O N FCS2 T RefSel R RefAlign O L AHRD MHR LOCK HOLDOVER ...

Page 23

... Two additional bits AHRD and MHR support recovery from Auto Holdover mode and they are described in section 3.2.4. ZL30407 Filtering Characteristic Table 3 - Filter Characteristic Selection Input Reference Table 4 - Reference Source Select 23 Zarlink Semiconductor Inc. Data Sheet ...

Page 24

... MCFC31, MCFC30, MCFC29, MCFC28, MCFC27, MCFC26, MCFC25, MCFC24, R/W MCFC23, MCFC22, MCFC21, MCFC20, MCFC19, MCFC18, MCFC17, MCFC16 R/W MCFC15, MCFC14, MCFC13, MCFC12, MCFC11, MCFC10, MCFC9, MCFC8 R/W MCFC7, MCFC6, MCFC5, MCFC4, MCFC3, MCFC2, MCFC1, MCFC0 Table 5 - ZL30407 Register Map 24 Zarlink Semiconductor Inc. Data Sheet Function ...

Page 25

... Reserved FCS2 = 0, FCS = 0 : Filter corner frequency set to 1.5 Hz. FCS2 = 0, FCS = 1 : Filter corner frequency set to 0.1 Hz. FCS2 = 1, FCS = 0 : Filter corner frequency set to 12 Hz. FCS2 = 1, FCS = 1 : Filter corner frequency set to 6 Hz. Table 6 - Control Register 1 (R/W) 25 Zarlink Semiconductor Inc. Data Sheet Default ...

Page 26

... When the FLIM bit goes high it will cause the LOCK status pin to go low, but it will not cause the LOCK status bit to go low. 1 RSV Reserved 0 RSV Reserved ZL30407 Functional Description Table 7 - Status Register 1 (R) 26 Zarlink Semiconductor Inc. Data Sheet ...

Page 27

... C34/C44 output and a logic high selects an 8.592 MHz clock. 5-0 RSV Reserved ZL30407 C20 0 -12 -9.2 9.2 12 C20 -7.4 -4.6 0 4.6 13.8 16.6 C20 -4.6 0 -16.6 -13.8 4.6 7.4 -15 - Functional Description Table 8 - Control Register 2 (R/W) 27 Zarlink Semiconductor Inc. Data Sheet Out of Range In Range Out of Range In Range Out of Range In Range 20 15 Frequency Offset [ppm] Default 000000 0 0 ...

Page 28

... Device Revision Number. These bits represent the revision number. Number starts from 0000. ZL30407 Functional Description Table 9 - Phase Offset Register 2 (R/W) Functional Description Table 10 - Phase Offset Register 1 (R/W) Functional Description Table 11 - Device ID Register (R) 28 Zarlink Semiconductor Inc. Data Sheet Default 0000 0 000 Default 0000 0000 ...

Page 29

... FCS2 = 0, FCS = 0 : Filter corner frequency set to 1.5 Hz FCS2 = 0, FCS = 1 : Filter corner frequency set to 0.1 Hz FCS2 = 1, FCS = 0 : Filter corner frequency set FCS2 = 1, FCS = 1 : Filter corner frequency set Table 12 - Control Register 3 (R/W) Functional Description Table 13 - Clock Disable Register 1 (R/W) 29 Zarlink Semiconductor Inc. Data Sheet Default 0 0 000 00 0 ...

Page 30

... AHDR bit should be set high permanently to prevent automatic return to Normal mode. 0 RSV Reserved Table 15 - Core PLL Control Register (R/W) ZL30407 Functional Description Table 14 - Clock Disable Register 2 (R/W) Functional Description 30 Zarlink Semiconductor Inc. Data Sheet Default 000 Default 00000 ...

Page 31

... PAFL This status bit is intended to provide software compatibility with the ZL30402 not required for new designs. Table 17 - Primary Acquisition PLL Status Register (R) ZL30407 Functional Description Functional Description 31 Zarlink Semiconductor Inc. Data Sheet Default 00000 000 ...

Page 32

... Master Clock Frequency Calibration. This byte contains the 15th to 8th bit of the Master Clock Frequency Calibration Register. Table 21 - Master Clock Frequency Calibration Register 2 (R/W) ZL30407 Functional Description Functional Description Functional Description Functional Description 32 Zarlink Semiconductor Inc. Data Sheet Default 00000 000 Default 00000 000 Default ...

Page 33

... The ZL30407 is designed to transition from one mode to the other driven by the internal State Machine or by manual control. The following examples present a couple of typical scenarios of how the ZL30407 can be employed in network synchronization equipment (e.g. timing modules, line cards or stand alone synchronizers). ZL30407 Functional Description 33 Zarlink Semiconductor Inc. Data Sheet Default 00000 000 ...

Page 34

... RefSel change NORMAL 00 Ref: OK AND Ref: OK-->FAIL AND MS2,MS1 = 00 {AUTO} HOLD- OVER RefSel Change 01 OR MS2,MS1 = 01 34 Zarlink Semiconductor Inc. Data Sheet Ref: FAIL-->OK AND MS2,MS1 = 00 AND AHRD = 1 AND MHR = 1 {MANUAL} OR Ref: FAIL-->OK AND MS2,MS1 = 00 AND AHRD = 0 MS2,MS1 = 00 {AUTO} {AUTO} AUTO ...

Page 35

... NORMAL 00 Ref: OK AND Ref: OK-->FAIL AND MS2,MS1 = 00 MS2,MS1 = 00 {AUTO} HOLD- OVER RefSel Change 01 OR MS2,MS1 = 01 35 Zarlink Semiconductor Inc. Data Sheet Ref: FAIL-->OK AND MS2,MS1 = 00 AND AHRD = 1 AND MHR = 1 {MANUAL} OR Ref: FAIL-->OK AND MS2,MS1 = 00 AND AHRD = 0 {AUTO} {AUTO} AUTO HOLD- OVER ...

Page 36

... RefSel change NORMAL 00 Ref: OK AND Ref: OK-->FAIL AND MS2,MS1 = 00 MS2,MS1 = 00 {AUTO} HOLD- OVER When HOLDOVER 0-->1 01 then set MS2,MS1 = 01 the Holdover State 36 Zarlink Semiconductor Inc. Data Sheet Set AHRD = 1 to disable {AUTO} automatic return to Normal mode AUTO HOLD- OVER AHRD = 1 AND MHR = 0 ...

Page 37

... RefSel change NORMAL 00 Ref: OK AND Ref: OK-->FAIL AND MS2,MS1 = 00 {AUTO} HOLD- OVER RefSel Change 01 OR MS2,MS1 = 01 References 37 Zarlink Semiconductor Inc. Data Sheet Ref: FAIL-->OK AND MS2,MS1 = 00 AND AHRD = 1 AND MHR = 1 {MANUAL} OR Ref: FAIL-->OK AND MS2,MS1 = 00 AND AHRD = 0 MS2,MS1 = 00 {AUTO} {AUTO} AUTO HOLD- ...

Page 38

... Ref: OK AND Ref: OK-->FAIL AND MS2,MS1 = 00 {AUTO} HOLD- OVER RefSel Change 01 OR MS2,MS1 = 01 Figure 13 - Manual Reference Switching 38 Zarlink Semiconductor Inc. Data Sheet Ref: FAIL-->OK AND MS2,MS1 = 00 AND AHRD = 1 AND MHR = 1 {MANUAL} OR Ref: FAIL-->OK AND MS2,MS1 = 00 AND AHRD = 0 MS2,MS1 = 00 {AUTO} {AUTO} AUTO ...

Page 39

... A detailed description of this Master/Slave redundant timing architecture based on ZL30407 can be found in Application Note ZLAN-67 “Applications of the ZL30407 Master/Slave Application”. ZL30407 PRI ZL30410 SEC Line Card #m PRI ZL30410 SEC Line Card #n Backplane 39 Zarlink Semiconductor Inc. Data Sheet SONET/SDH Framer E3/DS3 MUX with Framers ...

Page 40

... ZL30407 Figure 15 - Power Supply Filtering 40 Zarlink Semiconductor Inc. Data Sheet C1, C2, C3, C4 0.1 µF (ceramic) C6 µF (ceramic Ferrite Bead = BLM21A601R (Murrata) GND C3 VDD FB VDD AVDD C6 C7 GND GND GND ...

Page 41

... DD I DDS V 0.7 V CIH DD V CIL 2 250 1.125 260 Zarlink Semiconductor Inc. Data Sheet Min. Max. Units -0.3 7.0 V -0.3 VDD+0 -55 125 qC 1000 mW 1500 V Typ. Max. Units 3.3 3 +85 qC Max. Units Notes 155 ...

Page 42

... Supply voltage and operating temperature are as per Recommended Operating Conditions. * Timing for input and output signals is based on the worst case conditions (over T ALL SIGNALS t IF, Figure 16 - Timing Parameters Measurement Voltage Levels ZL30407 and V A Timing Reference Points Zarlink Semiconductor Inc. Data Sheet Symbol Level Units ...

Page 43

... DWS t 5 DWH t DSL t CSS t RWS t t ADH ADS VALID ADDRESS t DRD VALID DATA t t DWH DWS VALID DATA Figure 17 - Microport Timing 43 Zarlink Semiconductor Inc. Data Sheet Max. Units Notes CSH ...

Page 44

... F0L t 119 F0D t 119 C4L t -3 C4D t 240 C2L t -3 C2D t C16L t C8L t C4L t C2L Figure 18 - ST-BUS and GCI Output Timing 44 Zarlink Semiconductor Inc. Data Sheet Max. Units Notes 125 247 ns 125 ns 125 ...

Page 45

... Supply voltage and operating temperature are as per Recommended Operating Conditions. F8o tc = 125 Ps C6o tc = 158.43 ns C1. 647.67 ns ZL30407 Symbol Min C6L t -4 C6D t 320 C1. C1. C6L C6D t t C1.5D C1.5L Figure 19 - DS1 and DS2 Clock Timing 45 Zarlink Semiconductor Inc. Data Sheet Max. Units Notes 328 ...

Page 46

... Note: Delay is measured from the rising edge of C155P clock (single ended) at 1.25 V threshold to the rising and falling edges of C19o clock at V ZL30407 Symbol Min. t 2.6 C155L t -1 C19DLH t -2 C19DHL t 23 C19H t C19DHL t C19H threshold T Figure 20 - C155o and C19o Timing 46 Zarlink Semiconductor Inc. Data Sheet Max. Units Notes 3 1. ...

Page 47

... R1.5D t 100 R2W t 255 272 R2D t 20 R19W R19D C19D R8W t t R1.5D R1. R2D R2W t R19W 47 Zarlink Semiconductor Inc. Data Sheet Units Notes R8D R19D C19D ...

Page 48

... S H Symbol Min C44H t 5 C11H t 13 C34H t 9 C8.5H t C44H t C11H t C34H t C8.5H Figure and DS3 Output Timing 48 Zarlink Semiconductor Inc. Data Sheet Max. Units Notes ns ns Max. Units Notes ...

Page 49

... NA -104 +104 -12 + 885 41 49 Zarlink Semiconductor Inc. Data Sheet Units Notes Hz/Hz 0.1 Hz Filter Hz/Hz 1.5 Hz Filter Hz/ Filter Hz/ Filter ppm Holdover stability is determined by stability of the 20 MHz Master Clock oscillator ppm The 20 MHz Master Clock oscillator set at 0ppm ...

Page 50

... UIpp 0.964 0.1 UIpp 0.643 0.01 UI 0.064 RMS 1.5 UIpp 9.645 Equivalent Limit in limit in UI time domain 0.07 UIpp 45.3 0.5 UIpp 324 50 Zarlink Semiconductor Inc. Data Sheet Units Notes ns G.813 Option 1 1.326 ms Ps sec ZL30407 Jitter Generation Performance Typ. Units Notes C155 Clock Output 0.325 ns P-P 0.408 ns P-P 0 ...

Page 51

... UIpp 1.12 0.30 0.5 UIpp 11.2 0.47 Equivalent Limit in limit in Typ. UI time domain C16, C8, C4 and C2 Clock Outputs 0.05 UIpp 24.4 0.56 51 Zarlink Semiconductor Inc. Data Sheet ZL30407 Jitter Generation Performance Units Notes C6 Clock Output ns P-P ZL30407 Jitter Generation Performance Units Notes C44 Clock Output ns P-P ns P-P ZL30407 Jitter Generation ...

Page 52

... UIpp 3.215 0.512 0.075 UIpp 0.482 0.390 0.5 UIpp 3.215 0.512 C16, C8, C4 and C2 Clock Outputs 0.05 UIpp 24.4 0.56 0.05 UIpp 32.4 0.93 52 Zarlink Semiconductor Inc. Data Sheet ZL30407 Jitter Generation Performance Units Notes C34 Clock Output ns P-P ZL30407 Jitter Generation Performance Units Notes C155 Clock Output ns P-P ns ...

Page 53

... UIpp 0.643 0.390 0.5 UIpp 3.215 0.512 C16, C8, C4 and C2 Clock Outputs 0.05 UIpp 24.4 0.56 0.1 UIpp 0.643 0.408 0.1 UIpp 0.643 0.458 53 Zarlink Semiconductor Inc. Data Sheet ZL30407 Jitter Generation Performance Units Notes C155 Clock Output ns P-P ns P-P C19 Clock Output ns P-P ns P-P ns P-P C155 Clock Output ...

Page 54

... UIpp 0.482 0.325 0.5 UIpp 3.215 0.448 0.1 UIpp 0.643 0.390 0.5 UIpp 3.215 0.512 0.075 UIpp 0.482 0.390 0.5 UIpp 3.215 0.512 54 Zarlink Semiconductor Inc. Data Sheet ZL30407 Jitter Generation Performance Units Notes C155 Clock Output ns P-P ns P-P C155 Clock Output ns P-P ns P-P C19 Clock Output ns P-P ...

Page 55

... C19o (19.44 MHz) 10 C34o (34.368 MHz) 11 C44o (44.736 MHz) 12 C155o (155.52 MHz) 13 F0o (8 kHz) 14 F8o (8 kHz) 15 F16o (8 kHz) ZL30407 Typ. Typ. ( 0.0042 2.71 0.0019 0.95 0.0037 0.92 0.0179 2.84 0.0081 0.99 0.0222 2.58 0.0295 2.64 0.0161 0.98 0.0125 0.64 0.0433 1.26 0.0546 1.22 0.0867 0.56 NA 0.44 NA 0.46 NA 0.45 55 Zarlink Semiconductor Inc. Data Sheet Notes ...

Page 56

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Page 57

... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...

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