am79c988a ETC-unknow, am79c988a Datasheet

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am79c988a

Manufacturer Part Number
am79c988a
Description
Quad Integrated Ethernet Transceiver Quiet
Manufacturer
ETC-unknow
Datasheet

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Am79C988A
Quad Integrated Ethernet Transceiver (QuIET™)
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
The Am79C988A Quad Integrated Ethernet Transceiver
(QuIET) device consists of four independent 10BASE-T
transceivers which are compliant with the IEEE 802.3
Section 14 ( Medium Attachment Unit for 10BASE-T
Cabling ) standard. When combined with AMD's
Integrated Multiport Repeater 2 (IMR2™) chip, the
QuIET device provides a system-level solution to
designing a managed 10BASE-T repeater.
The QuIET device includes on-chip filtering for both
transmit and receive functions, thus eliminating the
need for external filters. On-chip filtering meets IEEE
802.3 (Section 14.3) electrical requirements. The
QuIET device provides automatic polarity detection and
correction and can operate in either normal or full-
duplex mode.
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Four independent 10BASE-T transceivers
compliant with IEEE 802.3 Section 14
(10BASE-T MAUs)
Direct interface with AMD's Am79C983A IMR2™
repeater device
On-chip filtering
— Eliminates external transmit and receive filters
— Meets IEEE 802.3 (Section 14.3) electrical
— Enables port switching when used with the IMR2
requirements
device
PRELIMINARY
The QuIET device interfaces directly with the Pseudo
AUI (PAUI™) ports on the IMR2 (Am79C983A) device
and can also be connected to standard AUI ports. Com-
mand and status data are exchanged with the IMR2
device via a serial management interface. Port switch-
ing can be easily implemented with the IMR2/QuIET
chipset to move individual ports between multiple Ether-
net segments under software control.
For application examples on building fully-managed
repeaters using the QuIET and IMR2 devices, refer to
AMD’s IMR2 Technical Manual (PID 19898A).
The QuIET chip is packaged in a 44-pin plastic leaded
chip carrier (PLCC). The device is fabricated in CMOS
technology and requires a single 5-V supply.
Automatic polarity detection and correction
Serial management interface allows transfer of
command and status data between the QuIET
device and a controller (IMR2 or other device)
Standard Ethernet (Normal) and Full-Duplex
modes
Extended distance option to accommodate
lines longer than 100 meters
Test functions provided for Loopback, Link Test,
Reverse Polarity, and Jabber
44-pin PLCC CMOS device with a single 5-V
supply
Publication# 19880
Issue Date: November 1997
Rev: B Amendment/+2

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am79c988a Summary of contents

Page 1

... Enables port switching when used with the IMR2 device GENERAL DESCRIPTION The Am79C988A Quad Integrated Ethernet Transceiver (QuIET) device consists of four independent 10BASE-T transceivers which are compliant with the IEEE 802.3 Section 14 ( Medium Attachment Unit for 10BASE-T Cabling ) standard. When combined with AMD's Integrated Multiport Repeater 2 (IMR2™ ...

Page 2

... CLK RST QuIET Device PDO Squelch PDO Squelch PDO Squelch PDO Squelch Collision, Loopback, Jabber and Link Test Am79C988A TXD+ TXD[0]+ Line Driver and Wave-Shaping TXD- TXD[0]- RXD+ RXD[0]+ Line Receiver and Smart Squelch RXD- ...

Page 3

... PCnet™-32 Single-Chip 32-Bit Ethernet Controller Am79C970 PCnet™-PCI Single-Chip Ethernet Controller (for PCI bus) Am79C970A PCnet™-PCI II Full Duplex Single-Chip Ethernet Controller (for PCI bus) Am79C974 PCnet™-SCSI Combination Ethernet and SCSI Controller for PCI Systems Am79C988A 3 ...

Page 4

... CONNECTION DIAGRAM DVSS Am79C988A Am79C988A 39 DVSS RST 38 37 REXT TEST 36 35 DIR 34 CLK SDATA 33 32 DVDD 31 TXD3+ 30 TXD3- 29 AVSS 19880B-2 ...

Page 5

... Ports (4 Ports Ports TP PAUI PAUI TP PAUI TP PAUI TP Serial Interface PDO TXD+ TXD- PDI PCI RXD+ RXD- Am79C988 A SDATA DIR CLK RST Am79C988A 19880B-3 Twisted Pair Ports (4 Ports) Serial Management Interface 19880B-4 5 ...

Page 6

... Valid Combinations table list configurations planned to be JC\T supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combina- tions and to check on newly released combinations. Am79C988A OPTIONAL PROCESSING Blank = Standard processing TEMPERATURE RANGE C = Commercial (0˚C to +70˚C) ...

Page 7

... These pins should be decoupled and kept separate from the analog power plane Digital Ground Ground Pin These pins provide the ground reference for the digital portions of the QuIET circuitry. Note: All digital I/O pins are CMOS and TTL compatible. Am79C988A 7 ...

Page 8

... FUNCTIONAL DESCRIPTION Overview The Am79C988A Quad Integrated Ethernet Transceiver ™ (QuIET ) device consists of four independent 10BASE-T transceivers which are compliant with the IEEE 802.3 Sec- tion 14 ( Medium Attachment Unit for 10BASE-T Cabling ) standard. The QuIET device includes on-chip filtering for both transmit and receive functions, thus eliminating the need for external fi ...

Page 9

... No Jabber n 1 Jabber S Not used, logic HIGH Preamble The 01010 preamble is an indication to the IMR2 that the transceiver is a QuIET device. QuIET Device The QuIET device returns 0000. Am79C988A SSSSSSSS ...

Page 10

... This command sets the QuIET device either in Full-Du- plex or Normal mode. The default is Normal mode Am79C988A 3 0 Disable Extended Distance Option 1 Enable Extended Distance Option 0 Disable Link Test 1 Enable Link Test 3 0 Disable Link Pulse Transmit 1 ...

Page 11

... Command and Status Default Conditions Command Extended Distance Link Test Link Pulse Transmit Correct Polarity Loopback Test Transceiver Mode Selection CMOS/PAUI Mode Status Device Link Polarity Jabber Am79C988A Default Disabled Enabled Enabled Disabled Disabled Normal PAUI Mode Default QuIET Fail Correct No Error ...

Page 12

... Connection to CMOS Circuits The PAUI ports on the QuIET device can also drive CMOS loads for other devices, including switches. The PDO, PDI, and PCI signals connect directly to the CMOS device. Note that CMOS mode must be selected in the Management Command Frame. Am79C988A ...

Page 13

... PDI2 PCI2 PCI2 PDO3 PDO3 PDI3 PDI3 PCI3 PCI3 MCLK RST RST CLK Note: Common mode chokes may be required. Figure 3. IMR2 Device to QuIET Device Connection Am79C988A QuIET TXD0+ 110 TXD0- RXD0+ 100 RXD0- TXD1+ 110 TXD1- RXD1+ 100 RXD1- TXD2+ 110 ...

Page 14

... PDO PDI PCI PDO PDI PCI PDO PDI PCI PDO PDI PCI PDO PDI PCI PDO PDI PCI Figure 5. Port Switching Am79C988A QuIET Device 2 SDATA DIR CLK RST QuIET Device 1 SDATA DIR CLK RST QuIET Device 0 SDATA DIR CLK RST 19880B-8 ...

Page 15

... 1:1 DO+ 78 DO- 1:1 DI+ AUI 200 Port DI- 1:1 CI+ 200 CI- Figure 6. AUI to PAUI Connections Am79C988A 0.1 F PDO PDI QuIET Device PCI 10 K 19880B-10 15 ...

Page 16

... PAUI Mode PAUI Mode PAUI Mode PAUI Mode AV = MAX MAX DD AV <V < (Note 5 Sinusoid 5 MHz <f< 10 MHz Sinusoid 5 MHz <f< 10 MHz Sinusoid 5 MHz <f< 10 MHz Sinusoid 5 MHz <f< 10 MHz Am79C988A ). . . . . . . . . . . . . . . . . + Min Max Unit -0.5 0.8 V 2 0 ...

Page 17

... Sinusoid 5 MHz <f< 10 MHz Sinusoid 5 MHz <f< 10 MHz Sinusoid 5 MHz <f< 10 MHz Sinusoid 5 MHz <f< 10 MHz (Note (Note MHz MAX (Uses Twisted Pair Switching Test Current MHz MAX Am79C988A Min Max Unit 180 312 mV -312 -180 mV 80 175 mV -175 -80 mV -60 +60 mV ...

Page 18

... Input > V (Max) ASQ (Note 3) Input > V (Max) ASQ (Note 4) (Note 7) (Note 1) (Note 7) (Note 7) (Note 1) (Note 5) (Note 6) (Note 1) (Note 1) (Note 1) RR (Note 1) (Note 1) (Note 7) (Note 7) (Note 7) (Note 7) Am79C988A Min Max Unit 49.995 50.005 150 - s 15 ...

Page 19

... PDO pulses wider than (min) will maintain internal PDO carrier sense on; PDO pulses longer than (min) will be rejected; RXD pulses longer than (min) will maintain internal RXD carrier sense; RXD pulses longer than Am79C988A Min Max Unit - ...

Page 20

... Changing from from Don’t Care, Changing, Any Change State Permitted Unknown Does Not Center Apply Line is High- Impedance “Off” State tCLKF tCLK tCLKH tCLKL Figure 7. Clock (CLK) Timing tRST tPRST Figure 8. Reset Pulse Am79C988A KS00010 19880B-11 19880B-12 ...

Page 21

... PDI PDO RXD tCON PCI tPWKDO tTSD tTSD tTSD tDODISD Figure 9. Transmit Signals tPWORD tPWKRD tRSD Figure 10. Receive Signals tCOFF tCPER tCPW Figure 11. Collision Signals Am79C988A tTETD 19880B-13 tPWKRD VTHS+ VTHS- tRR tRETD tRF 19880B-14 19880B-15 21 ...

Page 22

... SWITCHING WAVEFORMS tPWLP PDO TXD PCI tJA tPERLP Figure 12. Transmit Link Beat Pulse 50% tJR Figure 13. Jabber Function Am79C988A 19880B- 50% 0V 19880B-17 ...

Page 23

... SDATA tSDHD DIR { SDATA -1 DIR { SDATA DIR SDATA Figure 15. Serial Interface SDATA Transmit and Start Receive tSDSU tSSHD tSSSU L2 L3 tSSDO tSSDO M2 M3 Figure 14. Serial Interface Waveforms TSDS TDDS (min) (max) Am79C988A E1 19880B-18 TDDS 19880B-19 23 ...

Page 24

... SWITCHING TEST CIRCUITS Test Pin Figure 17. Twisted Pair Switching Test Circuit VDD R Test Point 100pF 330* VSS R = 330 for PAUI 1k for SDATA *Not used for SDATA Figure 16. Switching Test Circuit TXD+ TP 110 TXD- TP Am79C988A 19880B-20 19880B-21 ...

Page 25

... Product names used in this publication are for identification purposes only and may be trademarks of their respective companies .062 .083 .042 .056 REF .009 .015 .090 .120 .165 .180 SIDE VIEW Am79C988A .500 .590 .630 .013 .021 SEATING PLANE 16-038-SQ PL 044 EC80 11.3. ...

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