am79c901a Advanced Micro Devices, am79c901a Datasheet

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am79c901a

Manufacturer Part Number
am79c901a
Description
Homephy Single-chip 1/10 Mbps Home Networking Phy
Manufacturer
Advanced Micro Devices
Datasheet

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Am79C901A
HomePHY™
Single-Chip 1/10 Mbps Home Networking PHY
DISTINCTIVE CHARACTERISTICS
n Fully integrated 1 Mbps HomePNA Physical
GENERAL DESCRIPTION
The Am79C901A HomePHY is a single-chip device
that contains both a physical layer (PHY) for 1 Mbps
data networking over existing residential telephone
wiring based on the specification published by
HomePNA and a physical layer for supporting the
IEEE 802.3 standard for 10BASE-T. The HomePHY
is targeted at embedded applications and has both
GPSI and MII-compatible interfaces.
The integrated HomePNA transceiver is a physical
layer device that enables data networking at speeds
up to 1 Mbps over existing residential phone wiring
regardless of topology and without disrupting
telephone (POTS) service.
The integrated Ethernet transceiver is a physical
layer device supporting the IEEE 802.3 standard for
10BASE-T. It provides all of the PHY layer functions
Layer (PHY) as defined by Home Phoneline
Networking Alliance (HomePNA)
specification 1.1
— Optimized for home networking applications
— Media Independent Interface (MII)-compatible
— In-band control features:
— Register programmable features:
— any1Home™ link detection:
over existing telephone wire
for connecting external Media Access
Controller (MAC)
Adjustable power and speed levels
32 bits of reserved in-band messaging piggy-
backed on Ethernet packet
Power control
Speed control
Performance registers
Optional control of Squelch algorithm
Major frame timing parameters programma-
ble: ISBI, AID ISBI, pulse width, inter-symbol
time
Indicates to the MAC that a valid home net-
working node has been detected
Detects a network failure and allows the
upper layer protocol to take corrective action
PRELIMINARY
Refer to AMD’s Website (www.amd.com) for the latest information.
n Fully integrated 10 Mbps Ethernet transceiver
n Compliant with HomePNA specification 1.1
n General Purpose Serial Interface (GPSI)/Serial
n Extensive programmable internal/external
n Extensive LED status support
n IEEE 1149.1-compliant JTAG Boundary Scan
n Very low power consumption
n +3.3 V power supply along with 5 V tolerant I/Os
n Available in 68-pin PLCC and 80-pin TQFP
n Industrial Temperature Support (-40 ºC to +85
required to support 10 Mbps data transfer speeds.
A compliant IEEE 1149.1 JTAG test interface for
board level testing is provided. The Am79C901A
PHY also provides on-chip LED drivers for collision,
link integrity, speed, activity, and power output.
The Am79C901A PHY is fabricated in an advanced
low power 3.3 V CMOS process to provide low
operating current for power sensitive applications.
T h e A m 7 9 C 9 0 1 A P H Y i s a v a i l a b l e i n t h e
commercial temperature range (0ºC to +70ºC) in
68-pin PLCC and 80-pin TQFP packages. The
A m 7 9 C 9 0 1 A a l s o s u p p o r t s t h e i n d u s t r i a l
temperature range (-40ºC to +85ºC) in the 80-pin
TQFP package. The industrial temperature range is
well suited to environments with enclosures with
restricted air flow or outdoor equipment.
— Comprehensive Auto-Negotiation
— IEEE 802.3u-compliant MII
— Full-duplex operation supported on the MII
— Optimized for 10BASE-T applications
Peripheral Interface (SPI)
loopback capabilities
test access port interface
enable broad system compatibility
— XTAL1 supports 3.3 V I/O only
— XTAL2 supports 1.0 V I/O only
packages
implementation
port with independent Transmit (TX) and
Receive (RX) channels
Publication# 22304
Issue Date: July 2000
Rev: C Amendment/0
º
C)

Related parts for am79c901a

am79c901a Summary of contents

Page 1

... The Am79C901A PHY also provides on-chip LED drivers for collision, link integrity, speed, activity, and power output. The Am79C901A PHY is fabricated in an advanced low power 3.3 V CMOS process to provide low operating current for power sensitive applications commercial temperature range (0º ...

Page 2

... 1Mbps HomePNA PHY JTAG Port Link Control Control Data Interface PHY Control & Registers 10BASE-T PHY Link Control Data Interface PHY Control & Registers Am79C901A Transmit Drive State Control Machine HRTXRXP/N Receive Analog State Front Machine End Transmit State TX± ...

Page 3

... Silence Interval (AID symbol Data Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Mode Interface Mbps HomePNA PHY Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 any1Home Link Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10BASE-T PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Twisted Pair Transmit Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Twisted Pair Receive Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Twisted Pair Interface Status Collision Detect Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Jabber Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Am79C901A 3 ...

Page 4

... SWITCHING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 SWITCHING TEST CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 GPSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10BASE-T Transmit Timing (GPSI 10BASE-T Receive Timing (GPSI 10BASE-T Transmit Clock Timing (GPSI 10BASE-T Receive Clock Timing (GPSI Mbps HomePNA Transmit Timing (GPSI Am79C901A ...

Page 5

... Mbps HomePNA Transmit Timing (MII Mbps HomePNA Receive Timing (MII Mbps HomePNA Clock Timing (MII MDC/MDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 10BASE-T PMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 1 Mbps HomePNA Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 External Clock (XTAL1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 PHYSICAL DIMENSIONS 068 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 PQT Am79C901A 5 ...

Page 6

... Figure 38. MII Management Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Figure 39. SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 Figure 40. 10 Mbps Transmit (TX±) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Figure 41. 10 Mbps Receive (RX±) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Figure 42. HomePNA PHY AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 Figure 43. JTAG (IEEE 1149.1) Test Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Figure 44. External Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Am79C901A ...

Page 7

... Table 49. TBR7: 10BASE-T Auto-Negotiation Next Page Register (Register .63 Table 50. TBR16: 10BASE-T Status and Enable Register (Register 16 Table 51. TBR17: 10BASE-T PHY Control/Status Register (Register 17 Table 52. TBR19: 10BASE-T PHY Management Extension Register (Register 19 .66 Table 53. TBR24: 10BASE-T Summary Status Register (Register 24 . Am79C901A 7 ...

Page 8

... Note: NC pins are reserved and should be left unconnected Am79C901 A HomePHY Am79C901A RX- 58 AVDD 57 RX+ 56 AVSS 55 TX- 54 AVDD ...

Page 9

... AVDD 10 PHY_SEL 11 DVDD 12 RX_ER 13 DVSS GM_MODE 14 TX_CLK/TXCLK 15 TX_EN/TXEN 16 TXD0/TXDAT 17 TXD1/SDI Note: NC pins are reserved and should be left unconnected Am79C901 A HomePHY Am79C901A RX- 57 AVDD 56 RX+ 55 AVSS 54 TX- 53 AVDD 52 TX+ 51 AVSS 50 IREF 49 AVDD 48 HRTXRXP ...

Page 10

... Pin Name No. Name 35 TDO 36 TCK 37 TMS 38 TDI 39 XCLK/XTAL 40 XTAL2 41 XTAL1 42 AVDD AVDD 45 AVSS 46 AVSS 47 HRTXRXN 48 AVDD 49 HRTXRXP 50 AVDD 51 IREF Am79C901A Pin Pin No. Name 52 AVSS 53 TX+ 54 AVDD 55 TX- 56 AVSS 57 RX+ 58 AVDD 59 RX RESET 62 TEN 63 MII/GPSI 64 PHY_AD 65 ISOLATE 66 MDIO/SDO 67 DVSS 68 MDC/SCLK ...

Page 11

... AVDD 44 AVSS 45 AVSS 46 HRTXRXN 47 AVDD 48 HRTXRXP 49 AVDD 50 IREF 51 AVSS 52 TX+ 53 AVDD 54 TX- 55 AVSS 56 RX+ 57 AVDD 58 RX Am79C901A Pin Pin No. Name RESET 64 TEN 65 MII/GPSI 66 PHY_AD 67 ISOLATE 68 MDIO/SDO 69 DVSS 70 MDC/SCLK 71 LED_LINK 72 LED_COL 73 LED_ACTIVITY 74 DVDD 75 LED_POWER 76 LED_SPEED 77 DVSS ...

Page 12

... RX_DV MII Receive Data Valid MDC MII Management Data Clock MDIO MII Management Data Input/Output CRS Carrier Sense COL Collision Pin Function Type Am79C901A Number of Driver Type Pins I – – – – ...

Page 13

... Test Data Out Power Supply DVDD Digital Power AVDD Analog Power DVSS Digital Ground AVSS Analog Ground Test Interface TEN Test Enable Pin Function Type Am79C901A Number of Driver Type Pins O OMII 1 I – – OMII 1 ...

Page 14

... RX_DV MII Receive Data Valid MDC MII Management Data Clock MDIO MII Management Data Input/Output CRS Carrier Sense COL Collision Pin Function Type Am79C901A Number of Driver Type Pins I – – – – ...

Page 15

... Test Data Out Power Supply DVDD Digital Power AVDD Analog Power DVSS Digital Ground AVSS Analog Ground Test Interface TEN Test Enable Pin Function Type Am79C901A Number of Driver Type Pins O OMII 1 I – – OMII 1 ...

Page 16

... PIN DESIGNATIONS Listed By Driver Type The following table describes the various types of out- put drivers used in the Am79C901A PHY. All I I values shown in the table apply to 3.3 V signaling. OH Driver Name LED TS OMII TSMII Note: For reference only. See DC specification for actual limits. ...

Page 17

... Not applicable DEVICE NUMBER/DESCRIPTION Am79C901A HomePHY Single-Chip 1/10 Mbps Home Networking PHY Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD JC, JC\T sales office to confirm availability of specific valid VC, VI combinations combinations. Am79C901A Valid Combinations and to check on newly released 17 ...

Page 18

... An internal pulse stretching circuit will ensure that the minimum output pulse is approximately 100 ms. LED_LINK LED_LINK Input This output is designed to directly drive an LED. LINK low indicates that a valid link has been detected on the currently active PHY. Am79C901A Interface PHY_SEL ISOLATE Source ...

Page 19

... SCLK. Output SDO SPI Serial Data Out ovi Am79C901A to the master device. To provide for a ro- bust interface, this data is driven on the rising edge of Output SCLK. MII Interface ...

Page 20

... TCK is the clock input for the boundary scan test mode operation. It can operate at a frequency MHz. TCK has an internal pull-up resistor. TDI Test Data In TDI is the test data input path to the Am79C901A PHY. The pin has an internal pull-up resistor. Output TDO Test Data Out TDO is the test data output path from the Am79C901A PHY ...

Page 21

... Scan Test Interface TEN Test Enable The test enable pin is for factory use only. It must be connected to V Clock Source 20-MHz Crystal 60-MHz Oscillator/ External CLK Source Am79C901A Input Output +3.3 V Power +3.3 V Power Ground Ground Input for normal operation ...

Page 22

... RESET operation. H_RESET Hardware Reset (H_RESET reset operation that has been initiated by the proper assertion of the RESET pin of the Am79C901A device. When the minimum pulse width timing as specified in the RESET pin description has been satisfied, an inter- nal reset operation will be performed. ...

Page 23

... SFD and the beginning of the data. RXCRS will fall after the last received symbol. Once RXCRS falls, RXCLK and TXCLK are toggled continuously for 96 cycles, after which the PHY returns to the Idle state Figure 2. RXPKT - RXCRS Asserted Figure 3. RXPKT - RXCRS Cleared Am79C901A 22304B-4 22304B-5 23 ...

Page 24

... At this time RXCLK starts toggling, thereby, shifting 32 bits of preamble and SFD back to the MAC. Sometime later, the TXCLK restarts as symbols get sent onto the wire in an analogous manner as RXCLK during packet reception Figure 4. TXPKT - TXEN Asserted Figure 5. TXPKT - RXCLK Active Am79C901A 22304B-6 22304B-7 ...

Page 25

... TXCLK and RXCLK keep toggling for approx- imately another 100 clock cycles, when the system returns to the Idle state Figure 6. TXPKT - TXEN Cleared Figure 7. TXPKT - CLS Asserted Am79C901A 22304B-8 22304B-9 25 ...

Page 26

... In this case, the SDO might generate AAAA under the additional clock bits. See Figure Address Error Code Figure 9. Operation of the SPI Interface Am79C901A 22304B- Data In Data Out 22304B-11 ...

Page 27

... Figure 10. SPI Read Operation Codes Address Error Code = Address Error Code = AAAA Am79C901A Data Don’t Care 10 D15………D0 Data Out D15...D0 Don’t Care 31 32 22304B- 22304B- ...

Page 28

... MII. The information is encapsulated in a frame format as specified in Clause 22 of the IEEE 802.3u standard and is shown in Table 5. Table 5. MII Control Frame Format OP PHYADD REGADD 10 AAAAA RRRRR 01 AAAAA RRRRR Am79C901A Data In Data Out 22304B-15 TA DATA ...

Page 29

... PHY’s address. A station management entity attached to multiple PHYs is required to have prior knowledge of the appropriate PHY address. For more information, see the IEEE 802.3 specification and the MII pin descriptions. Preamble Figure 14. MII Start of Transmission Am79C901A Data D 2 22304B-16 29 ...

Page 30

... TX_CLK TX_EN TXD data CRS RX_CLK RX_DV RXD data COL IPG 96 Bit Times data 55 If SEQ is enabled Figure 15. MII End of Transmission Am79C901A Idle 55 22304B-17 ...

Page 31

... During a receive operation, the reverse process is exe- cuted. When a HomePNA PHY frame is received by the PHY, the header is stripped off and replaced with the 4 octets of preamble and delimiter of the IEEE 802.3 Ethernet MAC frame specification and then passed on to the MAC layer. Am79C901A 31 ...

Page 32

... SYNC_START pulse and SYNC interval trans- mitting station, the COLLISION event is asserted as described in the Collisions section. Am79C901A Ethernet Packet ETHERNET MAC and DATA CRC Length ...

Page 33

... TIC=86 AID_Position_2 TIC=106 AID_Position_3 TIC=126 TIC=126 Figure 18. AID Symbol Receive Timing Table 7. Access ID Symbol Pulse Positions and Pulse Position Am79C901A AID Symbol 2 TIC=129 and TIC=0 22304B-19 AID Symbol 2 AID_GUARD_INTERVAL TIC=129 and TIC=0 22304B-20 Encoding TICs from Beginning of AID Symbol ...

Page 34

... AID symbols (1 through 6). Any pulses detected in the silence interval are consid- ered a COLLISION event for transmitting stations and are handled as described in the Collisions section. Data Symbols Data symbols encode data for a much higher transmis- sion rate, and they do not allow collision detection. Am79C901A ...

Page 35

... TIC from the previous one as de- fined in the Data Transmit Timing section. Data symbol intervals are therefore variable and depend on the encoded data. Receiver Pulse 1 Position 0 Position 1 Position n1 Figure 20. Receive Symbol Timing Am79C901A PULSE_POSITION_0 Nominal Data Value Rate (in TICs) 0.7 Mbps 44 1.0 Mbps 28 ...

Page 36

... Management messages from a local management entity. Data stream from MAC controller Awaiting coding and transmission These select position These select position These select position 17 Figure 21. RLL 25 Coding Tree Am79C901A F 22304B-23 ...

Page 37

... Thus, the any1Home Packet provides link indication that the MAC requires for compliance to the Microsoft PC98, PC99, and HomePNA revision 1.1 requirements without utilizing resources from the upper layers of the system protocol Am79C901A Command Function 0 = version Set to low-power transmit mode Set to high-power transmit mode. ...

Page 38

... The receiver squelch level drops to half its threshold value after un- squelch to allow reception of minimum amplitude sig- nals and to mitigate carrier fade in the event of worst case signal attenuation and crosstalk noise conditions. Am79C901A Clock Data Manchester Decoder Squelch ...

Page 39

... Twisted Pair Interface Status The Am79C901A device will power up in the Link Fail state. The Auto-Negotiation algorithm will apply to allow it to enter the Link Pass state. In the Link Pass state, receive activity which passes the pulse width/amplitude requirements of the RX± inputs will cause the PCS Control block to assert the Carrier Sense (CRS) signal at the MII interface ...

Page 40

... In addition to the minimum IEEE 1149.1 requirements (BYPASS, EXTEST, and SAMPLE instructions), two additional instructions (IDCODE and TRI_ST) are provided to further ease board-level testing. All unused instruction codes are reserved. See Table 12 for a sum- mary of supported instructions. Am79C901A Driver Pulse Indication Mode Stretch ...

Page 41

... Am79C901A Cell Pin 1 Cell Name Type No. XTAL_SEL_L IN 39 CRS IN 32 CRS OUT 32 CRS_COL_OEN CO – COL IN 30 COL OUT 30 TXD3_CSN IN 28 TXD2 IN 27 TXD1_SDI IN 25 ...

Page 42

... Boundary register is 54 bits long. Data path starts from TDI to cell 53, cell 0 to TDO OUT 5 Cell Pin 1 Type No OUT OUT OUT OUT 66 CO – Am79C901A ...

Page 43

... USER ACCESSIBLE REGISTERS The Am79C901A PHY has two types of user regis- ters: 1 Mbps HomePNA PHY management registers (HPRs) and 10BASE-T PHY management registers (TBRs). Table 16. 1 Mbps HomePNA PHY Management Registers (HPRs) Register Address Symbol 0 HPR0 Control Register 1 HPR1 Status Register ...

Page 44

... PHY Control bit Electrically isolates PHY from the MII/GPSI 0 = Normal operation 1 = Restart Auto-Negotiation 0 = Normal operation ** Self Clearing 1 = Full-Duplex (for Loopback test only Half-Duplex 1 = Enable COL test signal 0 = Disable COL test signal Write as 0, ignore on read Am79C901A Default Read/ Value Write (hex) R ...

Page 45

... PHY is able to perform Auto-Negotiation 0 = PHY is not able to perform Auto-Negotiation 1 = Link Link is down This bit will be RESET (latched low and re-enabled on Read Jabber condition detected 0 = Normal operation 1 = Extended Register capability 0 = Basic Register Set capability Am79C901A Default Value Read/Write (hex ...

Page 46

... PHY_ID LSB (15-10) 15:10 9:4 PHY_ID LSB (9-4) 3:0 PHY_ID LSB (3- Description Most significant bytes of the PHY_ID (Bits 3-18) Description IEEE Address (Bits 19-24) Manufacturer’s Model Number Revision Number Am79C901A Default Read/ Value Write (hex) R 0000 Read/ Default Write Value (hex ...

Page 47

... HPR4: HomePNA PHY Auto-Negotiation Advertisement Register (Register 4) This register contains the advertised ability of the Am79C901A device. The purpose of this register is to advertise the technology ability to the link partner de- Table 21. HPR4: HomePNA PHY Auto-Negotiation Advertisement Register (Register 4) Bits Name When set, the device wishes to engage in next page exchange. If ...

Page 48

... Auto- Negotiation has successfully completed, as indicated by bit 5 in HPR1 the Next Page exchange is used, after the Page Received (bit 1 of HPR6) has been set to logic one. (Register 5) Description (Register 5) Description Am79C901A Default Value Read/Write (hex ...

Page 49

... Next Page Am79C901A device channel next page request 14 Reserved 13 Message Page Am79C901A device channel message page request 1 = Am79C901A device channel can comply with the request 12 Acknowledge Am79C901A device channel cannot comply with the request Toggle Am79C901A device channel toggle bit ...

Page 50

... Power down 0 = Normal operation (This bit is controlled by the HPR0, bit 11) Reads will produce undefined results 1 = Device is currently in High speed 0 = Device is currently in Low speed 1 = Device is currently in High power 0 = Device is currently in Low power Reads will produce undefined results Am79C901A Default Read/ Value Write (hex) R/W 0 R/W ...

Page 51

... A non-null transmitted PCOM will set the TxPCOM Ready bit in the Event Status Register (HPR26). An access to any of the two TxPCOM words will clear the TxPCOM Ready bit in the ISTAT register. Am79C901A Default Value Read/Write (hex) ...

Page 52

... PEAK measurement (HPR25, bits 7:0), this value is loaded into the NOISE Level register HPR25, bits 15:8. If the input NOISE measurement (HPR25, bits 15:8) exceeds the PEAK measurement (HPR25, bits 7:0), this value is loaded into the NOISE Level register HPR25, bits 7:0. Am79C901A Default Value Read/Write (hex) R 0000 ...

Page 53

... NOISE count every 50 ns. When adaptation is disabled, this register may be written to and is used to generate both the SLICE_LVL_NOISE and SLICE_LVL_DATA signals. This is a measurement of the peak level of the last valid (non-collision) AID received. Am79C901A Read/ Default Write Value R/W F4 ...

Page 54

... Status is cleared by writing remote command has been sent. Status is cleared by writing a 0. Description This value defines the number of TCLKs (116.6 ns) separating AID symbols. This value defines the number of TCLKs (116.6 ns) separating AID symbol 0. Am79C901A Default Read/ Value Write (hex ...

Page 55

... This value defines the number of pulses that will be driven onto the HRTXRX_P pin. Description Reserved. Must be written as 0. Read = X. Defines the drive level that will be utilized in the High Power mode. Defines the drive level that will be utilized in the Low Power mode. Am79C901A Default Read/ Value Write (hex) R/W 2C ...

Page 56

... Force_Link_Valid 6:0 Reserved 10BASE-T PHY Management Registers (TBRs) The Am79C901A home networking device supports the MII basic register set and extended register set. Both sets of registers are accessible through the MII management interface or via the SPI interface. As specified in the IEEE standard, the basic register set- Status Register (Register 1) ...

Page 57

... Enable Auto-Negotiation 0 = Disable Auto-Negotiation 1 = Power down 0 = Normal operation 1 = Electrically isolates PHY from the MII/GPSI 0 = Normal operation 1 = Restart Auto-Negotiation 0 = Normal operation 1 = Full-Duplex 0 = Half-Duplex 1 = Enable COL signal test 0 = Disable COL signal test Write as 0, ignore on read Am79C901A Default Read/Write Value (Note 1) (hex R/W ...

Page 58

... Remote fault detected remote fault detected 1 = PHY able to auto-negotiate PHY not able to auto-negotiate 1 = Link Link is down 1 = Jabber condition detected jabber condition detected 1 = Extended register capabilities 0 = Basic register set capabilities only Am79C901A Default Read/Write Value (Note 1) (hex ...

Page 59

... Table 44. Description IEEE Address (bits 3-18); Register 2, bit 15 is MSB of PHY Identifier Description IEEE Address (bits 19-24) Manufacturer’s Model Number (bits 5-0) Revision Number (bits 3-0); Register 3, bit 0, is LSB of PHY Identifier Am79C901A Read/ Write Default Value (hex) R 0000 Read/ Write Default Value (hex) ...

Page 60

... This bit advertises Half-Duplex capability for the Auto-Negotiation 10BASE-T 5 process. Setting this bit advertises Half-Duplex capability. Clearing this bit does not advertise Half-Duplex capability. The 10BASE-T PHY of the Am79C901A home networking device 4:0 Selector Field is an 802.3 compliant device ...

Page 61

... Auto- Negotiation has successfully completed, as indicated by bit 5 in TBR1 the Next Page exchange is used after the Page Received (TBR6, bit 1) has been set to logic one. See Table 46 and Table 47. Description Description Am79C901A Read/ Default Value Write (hex ...

Page 62

... Reserved 13 Message Page Am79C901A device channel message page request 1 = Am79C901A device channel can comply with the request 12 Acknowledge Am79C901A device channel cannot comply with the request 11 Toggle Am79C901A device channel toggle bit 10:0 Message Field Message code field Reserved Registers (Registers 8-15, 18, 20-23, and 25-31) ...

Page 63

... Duplex Mode has changed on a port change in Duplex mode 1 = Auto-Negotiation status has changed on a port change in Auto-Negotiation status 1 = Speed status has changed on a port change 1 = Indicates a change in status of any of the above interrupts 0 = Indicates no change in Interrupt status Am79C901A Read/ Default Value Write (hex R/W 0 ...

Page 64

... TBR17: 10BASE-T PHY Control/Status Register (Register 17) This register is used to control the configuration of the 10 Mbps PHY of the Am79C901A home networking device. See Table 1. Table 1. TBR17: 10BASE-T PHY Control/Status Register (Register 17) Bits Name 15:14 Reserved 13 Force Link Good Enable 12 Disable Link Pulse 11 SQE_TEST Disable ...

Page 65

... Last management frame was valid PHY Address defaults to 000X1 X = Value on pin PHY_ADD (i.e., 00001 or 00011) register access can convey. The Summary Status regis- ter indicates the following: Link Status, Full-Duplex Sta- tus, Auto-Negotiation Alert, and Speed. See Table 3. Description Am79C901A Default Value Read/Write (hex ...

Page 66

... Supply Voltages (V All inputs within the range Industrial (I) Devices Temperature (TA - +85 C Supply Voltages (V All inputs within the range Operating ranges define those limits between which the functionality of the device is guaranteed. Am79C901A ) . . . . . . . . . . . . . ...

Page 67

... IPG Maximum DD Transmitting maximum packets at minimum IPG Maximum Maximum MHz (Note MHz (Notes MHz (Note and transformer state. Am79C901A Min Max Units 2 2.5 V VDD 0.8 V 0.4 V 2.4 V 1.55 1.98 V 300 520 mV 150 300 ...

Page 68

... May Change from Don’t Care, Any Change Permitted Does Not Apply Figure 1. Normal and Tri-State Outputs Am79C901A OUTPUTS Will be Steady Will be Changing from Will be Changing from Changing, State Unknown Center Line is High- Impedance “ ...

Page 69

... Note: Not tested. TXCLK TXEN RXCRS TX± End of Packet TXDAT, TXEN Figure 2. 10 Mbps Transmit Timing (GPSI Parameter Description edge edge Am79C901A Min Max Unit 10 – – ns 240 360 ns 0 130 ns 0 130 ns 300 – ...

Page 70

... RXCRS de-assert latency from EOP PD RXCLK RX± CLS RXCRS RXDAT Figure 3. 10 Mbps Receive Start of Packet Timing (GPSI Parameter Description Start of Packet Am79C901A Min Max Unit 200 300 ns 200 300 ns 320 430 ns – ...

Page 71

... RXCLK pulse width LOW 20 t PWL TXCLK, RXCLK Figure 5. 10 Mbps Transmit and Receive Clock Timing (GPSI End of Packet Parameter Description Parameter Description 18 19 Am79C901A 22304B-28 Min Max Unit 99.99 100. Min Max Unit 99 ...

Page 72

... Note: Not tested. TXCLK TXDAT 24 TXEN HRTXRXP/N± CLS Figure 6. 1 Mbps HomePNA Transmit Timing (GPSI Parameter Description 26 27 SYNC AID PCOM 28 Am79C901A Min Max Unit 12 – 10 – 10 – 10 – 200 500 – 120 23 25 ...

Page 73

... RXCRS inactive to CLS inactive clocked into MAC (Note Note: Not tested. RXCLK RXDAT SYNC HRTXRXP/N RXCRS 30 CLS Figure 7. 1 Mbps HomePNA Receive Timing (GPSI Parameter Description DATA AID DATA Am79C901A Min Max Unit 650 850 ns 15.98 16.10 s – 200 ns 29 DATA ...

Page 74

... TXCLK, RXCLK pulse width LOW PWL Note: During AID interval, RXCLK and TXCLK stop for up to 140 s. TXCLK, RXCLK Figure 8. 1 Mbps HomePNA Clock Timing (GPSI Parameter Description Am79C901A Clock Period Unit 583.3 ns 115.5 ns 467.8 ns 233.3 ns 115.5 ns 117 ...

Page 75

... TX_CLK TX_EN CRS TX± End of Packet TXD, TX_EN Parameter Description edge edge Figure 9. 10 Mbps Transmit Timing (MII) Am79C901A Min Max 10 – 0 – 240 360 0 430 0 430 1200 – Start of Packet 22304B-33 Unit ...

Page 76

... Note: RXD not tested. RX_CLK RX± COL CRS RXD, RX_DV Figure 10. 10 Mbps Receive Start of Packet Timing (MII Parameter Description Start of Packet Am79C901A Min Max Unit 200 300 ns 200 300 ns 625 1275 ns – ...

Page 77

... AC CHARACTERISTICS (CONTINUED) 10BASE-T Receive Timing (MII) (Continued) RX_CLK RX± COL CRS RX_DV Figure 11. 10 Mbps Receive End of Packet Timing (MII End of Packet Am79C901A 22304B-35 77 ...

Page 78

... PWH 59 t RX_CLK pulse width LOW PWL TX_CLK, RX_CLK Figure 12. 10 Mbps Transmit and Receive Clock Timing (MII Parameter Description Parameter Description 57 58 Am79C901A Min Max Unit 399.6 400.4 ns 180 220 ns 180 220 ns Min Max Unit 399 ...

Page 79

... Note: Not tested. TX_CLK TXD, TX_EN TX_EN HRTXRXP/N± COL Figure 13. 1 Mbps HomePNA Transmit Timing (MII Parameter Description edge edge 62 64 SYNC AID PCOM 65 Am79C901A Min Max Unit 10 – – ns 200 500 ns – 120 s 63 ...

Page 80

... PD Note: Not tested. RX_CLK RXD, RX_DV SYNC HRTXRXP/N± CRS 69 COL Figure 14. 1 Mbps HomePNA Receive Timing (MII Parameter Description DATA AID DATA Am79C901A Min Max Unit 650 850 ns 15.98 16.10 s – 200 ns 68 DATA ...

Page 81

... TX_CLK, RX_CLK pulse width LOW PWL Note: During AID interval, RX_CLK and TX_CLK stop for up to 140 s. TX_CLK, RX_CLK Figure 15. 1 Mbps HomePNA Clock Timing (MII Parameter Description 74 75 Am79C901A Clock Period Unit 2333.34 ns 1165 ns 1168 ns 933.33 ...

Page 82

... MDIO input hold time from MDC MDC to high impedance Z MDC MDIO Parameter Description edge edge edge Figure 16. MII Management Timing Am79C901A Min Max Unit 400 – ns 160 – ns 160 – 300 ns 8 – – ...

Page 83

... PZD CS 91 SCLK 93 SDI SDO Parameter Name Min 400 160 160 valid Figure 17. SPI Timing Am79C901A Max Unit – ns – ns – – ns – – – – ...

Page 84

... Figure 19. 10 Mbps Receive (RX±) Timing Diagram Test Conditions |V | > (Note 1) IN THS (min) will maintain internal Carrier Sense on. RX± pulses wider than t 100 100 100 Am79C901A Min Max Unit 250 375 ns 136 200 ns (max) PWKRD 99 ...

Page 85

... Measurements across HRTXTXP and HRTXTXN, differentially measured, with Parameter Name Conditions Low Power High Power Low Power High Power = 3.3 V, 25°C. CC 105 103 104 Figure 20. HomePNA PHY AC Waveform Am79C901A Typical Units 133 1.00 V 2.00 1. ...

Page 86

... Note: 1. Not tested; parameter guaranteed by design characterization. TCK TDI, TMS TDO Figure 21. JTAG (IEEE 1149.1) Test Signal Timing Parameter Name 111 110 110 110 112 113 114 115 Am79C901A Min Max Unit ns 100 – 45 – – – – ...

Page 87

... Cycle LOW time PWL XTAL1 Reset Symbol Parameter Description t RESET to RESET Parameter Description 119 120 Figure 22. External Clock Timing Am79C901A Min Max Unit 16.665 16.669 CYCLE CYCLE 0 0 CYCLE CYCLE ...

Page 88

... PHYSICAL DIMENSIONS* PL 068 Plastic Leaded Chip Carrier (measured in inches) *For reference only. BSC is an ANSI standard for Basic Space Centering Am79C901A ...

Page 89

... PHYSICAL DIMENSIONS* PQT 80 Thin Plastic Quad Flat Pack (measured in millimeters) *For reference only. BSC is an ANSI standard for Basic Space Centering Am79C901A 89 ...

Page 90

... AlertIT, any1Home, eIMR, eIMR+, GigaPHY, HIMIB, HomePHY, IMR2, MACE, Magic Packet, NetPHY, PCnet, PCnet-Home, QuEST, and QuIET are trademarks of Advanced Micro Devices, Inc. RLL25 is a trademark of Tut Systems, Inc. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 22304C Am79C901A ...

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