am79c30a Advanced Micro Devices, am79c30a Datasheet
am79c30a
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am79c30a Summary of contents
Page 1
... Provides multiframe support BLOCK DIAGRAM CAP1 CAP2 AINA Main Audio AREF AINB Processor (MAP) EAR1 EAR2 (Am79C30A LS1 Only) LS2 XTAL1 Oscillator (OSC) XTAL2 MCLK This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product ...
Page 2
... The Am79C30A/32A processes the ISDN basic rate bit stream, which consists of B1 (64 Kbit/s), B2 (64 Kbit/s), and D (16 Kbit/s) channels. The B channels are routed to and from different sections of the Am79C30A/32A 2 — Programmable sidetone level — Programmable DTMF, single tone, progress tone, and ringer tone generation — ...
Page 3
... RSRVD = Reserved pin; should not be connected externally to any signal or supply. 44-Pin PLCC Am79C30A 44-Pin PLCC Am79C32A Am79C30A/32A Data Sheet 39 LOUT1 38 LOUT2 INT 34 XTAL1 33 XTAL2 32 MCLK 31 SFS 30 SCLK 29 SBOUT 39 LOUT1 ...
Page 4
... A1 Note: Pin 1 is marked for orientation purposes. 4 44-Pin TQFP Am79C30A 44-Pin TQFP Am79C32A Am79C30A/32A Data Sheet 33 LOUT1 32 LOUT2 INT 28 XTAL1 27 XTAL2 26 MCLK 25 SFS 24 SCLK 23 SBOUT 33 LOUT1 32 LOUT2 31 AV ...
Page 5
... Digital Subscriber Controller (DSC) device ISDN Data Controller (IDC) device Valid Combinations list configurations planned to be sup- ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am79C30A/32A Data Sheet Valid Combinations 5 ...
Page 6
... A2, A1, and A0 signals select source and destination registers for read and write operations on the data bus. CS Chip Select (Input) CS must be Low to read or write to the Am79C30A/ 32A. Data transfer occurs over the bidirectional data lines (D7–D0). D7–D0 Data Bus (Bidirectional with High-Impedance State) The eight bidirectional data bus lines are used to ex- change information with the microprocessor ...
Page 7
... The MCLK output is available for use as the system clock for the microprocessor. MCLK is derived from the 12.288-MHz crystal via a programmable divider in the Am79C30A/32A which provides the following MCLK output frequencies: 12.288, 6.144, 4.096, 3.072, 1.536, 0.768, and 0.384 MHz. XTAL1, XTAL2 ...
Page 8
... The CS and WR pins are both pulled Low at the same time, as would occur during a normal write operation from the microprocessor to the DSC cir- cuit. No data will be transferred by this operation. • The HSW hookswitch pin changes state, and the hookswitch interrupt is enabled. Am79C30A/32A Data Sheet ...
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... MCLK frequency = 6.144 MHz DLC receiver abort disabled DLC receiver abort enabled DLC transmitter abort disabled DLC transmitter abort enabled Am79C30A/32A Data Sheet Function 9 ...
Page 10
... Reserved Reserved 10 RESET Operation The Am79C30A/32A can be reset by driving the RESET pin High. When power is first supplied to the DSC/IDC circuit, a reset must be performed. This ini- tializes the DSC/IDC circuit to its default condition as defined in Table 3. ...
Page 11
... S-Interface B channels must be serviced. IR bits and 7, if set, indicate that a bit has been set in the associated status or error register. All of the interrupts generated by the Am79C30A/32A can be individually disabled. In the case of IR bit 7, the inter- rupt can also be masked by setting PPIER bit ...
Page 12
... PPSR bit 3 Monitor abort received PPSR bit 4 C/I channel 0, data change PPSR bit 5 C/I channel 1, data change PPSR bit 6 IOM-2 timing request 12 Am79C30A/32A Data Sheet Interrupt Mask DMR1 bit 0 DMR1 bit 1 DMR3 bit 0 DMR1 bit 3 DMR3 bit 1 DMR2 bit 0 DMR2 bit 1 DMR2 bit 2 ...
Page 13
... Microprocessor Interface (MPI) The Am79C30A/32A can be connected to any general purpose 8-bit microprocessor via the MPI. The MCLK from the Am79C30A/32A can be used as the clock for the microprocessor. The MPI is an interrupt-driven in- terface containing all the circuitry necessary for access to the internal programmable registers, status regis- ters, coefficient RAM, and transmit/receive buffers ...
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... STRF 15 PEAKX 16 PEAKR 17 Perform 15–16 1 FRAR SRAR1 TAR 4 DRLR 5 DTCR Am79C30A/32A Data Sheet Mode Address Byte Sequence R/W 21H One byte transferred R/W 20H One byte transferred R A1H One byte transferred R/W A2H One byte transferred R/W A3H One byte transferred One byte transferred ...
Page 15
... High and Low marks, and a frame recovery cir- cuit for frame synchronization. The receiver converts the received pseudo-ternary coded signals to binary before delivering them to the other blocks of the Am79C30A/32A. It also performs collision detection (E- and D-bit comparison) per the CCITT recommenda- Register Number ...
Page 16
... Multiframe S bit/Status buffer (MFSB) once the S-bit available bit (MFSB bit 5) is set. The S-data available bit is set to a logical 1 when the Am79C30A/32A has received five S bits (one S bit per S-interface frame) synchronized to the setting of the F -bit to a logical 1 and transferred them into the A MFSB ...
Page 17
... When loss of multiframe synchronization occurs, bit 7 of the Multiframe Register is set to a logical 0, and bit 7 of the Multiframe S bit/Status buffer is set to a logical 1. The Am79C30A/32A also terminates the re- ception of S bits and transmission of Q bits until multi- framing synchronization is re-established. ...
Page 18
... The LPR contains the priority level for D-channel ac- MFQB cess. Its default value after reset is 0. The D-channel access procedure of the Am79C30A/ 32A uses the priority level programmed in the LPR. The priority mechanism defined by the CCITT I-series rec- ommendations is fully implemented if the LPR is pro- grammed via the microprocessor to conform to the priority class of the Layer-2 frame to be transmitted ...
Page 19
... Reserved; must be set to logical 0 Notes: The F and F bits in LMR1 (bits 2 and 3) should be enabled during the activation procedure so the Am79C30A/32A can respond A with INFO 3. LMR1 bit 4 is used to transfer the signals PH-AR and Expiry of Timer from the microprocessor to the LIU (see CCITT I.430 state diagram— ...
Page 20
... This loopback is provided for maintenance purposes from the TE’s perspective. The Am79C30A/32A trans- mits D-channel bits to the NT where they are looped and transmitted back to the Am79C30A/32A in the E channel. The operation is normal except differences between the D and E channels do not halt the trans- mission ...
Page 21
... Ba (MAP), the contents of the MCRs would be: Port 1 Register Channel Connection MCR1 (LIU) MCR2 (LIU) MCR3 connect Am79C30A/32A Data Sheet Port 2 Bb (MPI) Ba (MAP) No connect 21 ...
Page 22
... Bb (MPI) The final data transfers are: B1 (LIU) receives Bb (MPI), Ba (MAP) receives Bb (MPI), Bb (MPI) receives Ba (MAP). Therefore, the data transfer from B1 (LIU (MPI) is lost in the arrangement proposed in MCR2. Am79C30A/32A Data Sheet B1 LIU B2 09893H-3 Port 2 Bb (MPI) Ba (MAP) ...
Page 23
... Reserved, must be set to logical 0 7 Reserved, must be set to logical 0 Table 19. MUX Control Register 4 Logical 0 (Default Value) Reserved, must be set to logical bit reversal (MSB transmitted/received first bit reversal (MSB transmitted/received first) Reserved, must be set to logical 0 Reserved, must be set to logical 0 Am79C30A/32A Data Sheet 23 ...
Page 24
... Ringer are disabled. Decimators, BPF (A) DTMF GEN. R* Tone* (C) Ringer Maximum Step 6.0 dB –6 dB 1.5 dB Am79C30A/32A Data Sheet PEAKX Ba channel X* GX* COMP* MUX Transmitter Receiver Sidetone Gain* Ba channel from + GER* GR* EXP* MUX PEAKR Tone* (B) Gen. 09893H-4 ...
Page 25
... The data extraction point for the transmit path is after the X filter. 4. The data extraction point for the receive path is im- mediately following the expander. 5. The compressed data from the transmit and receive paths is presented using the same compression algorithm. Am79C30A/32A Data Sheet 25 ...
Page 26
... Tone Ringer uses the amplitude programmed in ATGR2. Common frequency values are listed in Table 22. The FTGR codes to obtain DTMF dialing output fre- quencies are listed in Table 21. Table 21. DTMF Codes 9BH ABH 1209 1336 Am79C30A/32A Data Sheet BFH D3H 1477 1633 ...
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... STR are simultaneously enabled, priority 17 is given to the STR connection. The STR is available for both the DSC and IDC circuits. A legal value must be 16 programmed in the STRF register before the STR is 15 enabled. Am79C30A/32A Data Sheet Hex Code –18 37 –16 32 –14 31 – ...
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... DE 7.0 EF 7.5 9C 8.0 9D 8.5 AE 9.0 CD 9.5 DF 10.0 29 10.5 AB 11.0 FF 11.5 BD 12.0 EF 12.5 CE 13.0 CD 13.4 99 14.0 4C 14.5 DD 15.0 DD 15.5 EF 15.9 1B 16.6 42 16.9 DD 17.5 18.0 Am79C30A/32A Data Sheet Hex Code MSB LSB ...
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... D3 –6.0 A2 –5.5 1B –5.0 3B –4.5 C3 –4.0 F2 –3.5 BA –3.0 CA –2.5 1D –2.0 5A –1.5 22 –1.0 12 –0 Am79C30A/32A Data Sheet Hex Code MSB LSB ...
Page 30
... DSC is capable of performance beyond these rec- 08 ommended ranges. (GA and ASTG are not imple- mented in DSP and are limited to their stated range and step size.) Table 28 lists guaranteed ranges, while Table 29 shows the limits by design. Am79C30A/32A Data Sheet and the re Likewise desirable that P , and a ...
Page 31
... This test allows the MAP analog and dig- ital to be tested using a local signal source. MAP Digital Loopback 1 A0 This loopback mode connects the interpolator output to the decimator input in place of the ADC output. This mode allows verification from the S Interface or micro- Am79C30A/32A Data Sheet ...
Page 32
... Bytes Mnemonic GER 2 STGR 2 FTGR 2 ATGR 1 MMR 1 STRA 1 STRF 1 PEAKX 1 PEAKR Am79C30A/32A Data Sheet Table 32. Default Values Default Response Disabled (0 dB, Flat) Disabled (0 dB, Flat) Disabled (0 dB, Gain) Disabled (0 dB, Gain) Disabled (0 dB, Gain) Disabled (–18 dB, Gain) ...
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... STG gain = –18 dB* Digital loopback #1 at MAP disabled Table 34. Map Mode Register 2 Logical 0 (Default Mode) AINA selected EAR1/EAR2 selected DTMF disabled Tone generator disabled Tone ringer disabled High pass filter enabled ADC auto-zero function enabled Reserved, must be Logical 0 Am79C30A/32A Data Sheet 33 ...
Page 34
... 5.00 V Bits 0–3 Reserved must be written to 0 Am79C30A/32A Data Sheet Approximate Power into 50 ohms –27 dB 0.25 mW –24 dB 0.5 mW –21 dB 1.0 mW –18 dB 2.0 mW –15 dB 4.0 mW –12 dB 8.0 mW –9 dB 16.0 mW –6 dB 31.25 mW – ...
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... E5 272.7 424.8 72 271.2 421.1 B9 269.7 417.4 DC 268.2 413.8 EE 266.7 410.3 77 265.2 406.8 BB 263.7 403.4 DD 262.3 400.0 6E 260.9 396.7 37 259.5 Am79C30A/32A Data Sheet Counter Frequency Value (Hz) F7 247.4 FB 246.2 FD 244.9 7E 243.7 BF 242.4 5F 241.2 2F 240.0 97 238.8 CB 237.6 65 236.5 32 235.3 99 234.2 CC 233.0 66 231 ...
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... S Interface, the S-Interface frame struc- ture is impressed upon the D-channel frame structure (LAPD). Zero Insertion/Deletion When transmitting, the DLC examines the frame con- tent between the opening and closing flags. To ensure Am79C30A/32A Data Sheet Counter Frequency Value (Hz) E4 192 ...
Page 37
... Table SAPI TEI CONTROL FCS 8 bits 16 bits 4 5,6 CONTROL INFORMATION 8 bits N bits 4 5 … C/R = Command/Response Field bit TEI = Terminal Endpoint Identifier Am79C30A/32A Data Sheet OCTET 2 OCTET 3 FLAG Minimum Packet 01111110 7 FLAG FCS General 01111110 16 bits N N – 1 09893H-4 37 ...
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... D-channel Sta- tus Register 1 (DSR1). The DLC then receives the first two bytes (the two address bytes). If address recogni- tion is enabled, the Am79C30A/32A issues a Valid Ad- dress interrupt if a match between the programmed values and the received address is detected match is detected and address recognition is enabled, the DLC ignores the packet ...
Page 39
... Am79C30A/32A receives the first two bytes, issues an End of Address interrupt, and receives the packet. Both a Valid Address and an End of Ad- dress interrupt set Interrupt Register bit logical 1 and bit 0 of the D-channel Status Register 1 (DSR1 logical 1. The Valid Address/End of Address interrupt can be disabled via DMR3 bit 0 ...
Page 40
... The DLC alerts the microprocessor to this event by asserting the interrupt line (INT) and setting DER bit collision occurs during the trans- mission of an abort sequence, the interrupt is still is- sued. The collision detect interrupt can be masked by setting DMR2 bit logical 0. Am79C30A/32A Data Sheet ...
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... DCRB register), and a third packet is received. When this error occurs, DSR2 bit 2 is set to a logical 1 and the incoming packet is ter- minated (not received). Am79C30A/32A Data Sheet Number of Registers Mnemonic 4 FRAR 4 ...
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... Enable FRAR2/SRAR2 6 Enable FRAR3/SRAR3 7 Enable FRAR4/SRAR4 42 Table 39. D-Channel Mode Register 1 Logical 0 Disable interrupt (default value) Disable Transmit Address Register (default value) Disable interrupt (default value) Disable FRAR1/SRAR1 (default value) Disable FRAR2/SRAR2 (default value) Disable FRAR3/SRAR3 (default value) Disable FRAR4/SRAR4 Am79C30A/32A Data Sheet ...
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... Enable Transmit buffer Available interrupt (see DSR2 bit 4) 6 Enable Received Packet Lost interrupt (see DSR2 bit 2) 7 Enable FCS transfer to FIFO Table 40. D-Channel Mode Register 2 Table 41. D-Channel Mode Register 3 Am79C30A/32A Data Sheet Logical 0 (Default Value) Disable interrupt Disable interrupt Disable interrupt Disable interrupt Disable interrupt ...
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... Note: The receiver and transmitter thresholds can only be changed when the Am79C30A/32A is in Idle mode. Address Status Register — (ASR) — Read Only Address = Indirect 91H Bit Logical 1 0 FRAR1/SRAR1 address recognized 1 FRAR2/SRAR2 address recognized 2 FRAR3/SRAR3 address recognized ...
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... When the microprocessor reads DSR1 or when DTCR is loaded DTCR is loaded Am79C30A/32A Data Sheet Logical 0 (Default Value) No valid address Not end of packet Packet not being received No loopback in operation at Am79C30A/32A No loopback in operation at LIU D-channel back-off in operation No end-of-transmit packet or no transmission No transmit packet abort 45 ...
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... Receive packet not lost Last byte not transmitted Transmit buffer not available* Mark idle not detected Second packet not yet in FIFO Table 47. DSR2 Interrupts Am79C30A/32A Data Sheet Bit Reset When the microprocessor reads the DSR2 When DCRB is empty When the microprocessor reads ...
Page 47
... X Bits 7 and 2 reserved, must be written to 0 Bits 6–3 control attenuation of the analog sidetone path (ASTG) X Start of Second Received Packet In FIFO interrupt disabled X Start of Second Received Packet In FIFO interrupt enabled 0 Normal mode of FIFO operation 1 Extended mode of FIFO operation Am79C30A/32A Data Sheet 47 ...
Page 48
... OUT = Output Note: *The Am79C30A is a non-Layer-1 component when operated in the Slave mode; however, it has a microprocessor interface result required to change the direction of its I/O pins at certain times in order to communicate with both the upstream Layer-1 device and any downstream peripheral devices. In the IOM-2 Slave mode, the direction of data flow is reversed with respect to the DSC circuit during Sub-frame 0 and during the deactivated state ...
Page 49
... All data transmitted on the IOM-2 Interface via the SBOUT pin is transmitted MSB first, with the exception of D-channel data, which is transmitted LSB first. The receiver operates in a compatible way via the SBIN pin. MR,MX IC1 IC2 MON1 C/I IOM channel 1 Am79C30A/32A Data Sheet Bf 09893H-6 MR,MX TIC IOM channel 2 09893H-7 49 ...
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... TIC Bus The IOM-2 TIC bus control bits reside in the last byte to the IOM-2 Terminal mode frame (channel 2, byte 4). The bits and their definitions are shown in Figure BAC TBA2 TBA1 TBA0 E E S/G A/B 1 Am79C30A/32A Data Sheet ...
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... DU ence of the TIC bus provides D and C/I0 access to all downstream devices. For control slave applications, the DSC can disable all IOM-2 channel 1 communica- tions. B1, B2, D, MON0, C/10, IC1, IC2, MON1, C/I1, S/G(out), TIC(in) Figure 8. IOM-2 Master Mode Operation Am79C30A/32A Data Sheet upstream downstream 51 ...
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... SBOUT DSC SBIN DD Downstream # Downstream #2 DU Figure 9. IOM-2 Slave Mode Operation with Bus Reversal 52 stream devices via MONI and C/I1). D and C/I0 arbitra- tion provided by TIC bus capability. IC1, IC2, MON1, C/I1 B1, B2, D, MON0, C/I0, S/G(in), TIC(out) Am79C30A/32A Data Sheet U- transceiver DD DU upstream downstream ...
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... SBOUT DSC SBIN DD Downstream # Downstream #2 DU Figure 10. IOM-2 Slave Mode Operation without Bus Reversal downstream devices). D and C/I0 arbitration provided by TIC bus capability. B1, B2, D, MON0, C/I0, IC1, IC2, MON1, C/I1, S/G(in), TIC(out) Am79C30A/32A Data Sheet DSC Master SBOUT SBIN upstream downstream 53 ...
Page 54
... TIC bus by setting BAC=1. The S-transceiver then mirrors the incoming D bits into the E-channel, thus behaving as a normal NT with trans- parent D-channel handling. B1, B2, D, MON0, C/I0, IC1, IC2, MON1, C/I1, S/G(in), TIC(out) DD S-transceiver LT-S DU Am79C30A/32A Data Sheet U-transceiver Master DOUT/DD DIN/DU upstream downstream ...
Page 55
... Flow Control The transmitter is held off until the Monitor Receive Data Register is read, since MR is held active until the receive byte is read. The transmitter will not start the next transmission cycle until MR goes inactive. Am79C30A/32A Data Sheet 55 ...
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... General Case New Byte b. Abort Request from the Receiver Second Byte Third Byte ACK First Byte Second Byte c. Maximum Speed Case Figure 12. Monitor Handshake Timing Am79C30A/32A Data Sheet EOM ACK EOM Abort Request EOM ACK Third Byte 09893H-8 ...
Page 57
... Software sets Activation bit Notes: This diagram shows only the portions of the IOM-2 activation/deactivation procedures that are affected by the Am79C30A hardware. The C/I-channel software handshakes are not shown. Figure 13. IOM-2 Activation/Deactivation DSC/IDC Circuit as Upstream Device (Clock Master) Deactivation ...
Page 58
... To activate the inter- face from the downstream device, the processor sets the activation/deactivation bit in the PPCR1 register. This will force the Am79C30A to pull its data output pin (SBIN in this case, since the I/O pin definition is re- versed when talking to the upstream device) Low, causing the upstream device to start the IOM-2 clocks ...
Page 59
... C/I0 communication is still in progress and the BAC output remains 0 until software clears CITDR0.7. A priority scheme is included to prevent the DSC from dominating the bus. A new bus access will not be al- lowed until the device detects BAC bit set two successive frames. Am79C30A/32A Data Sheet 59 ...
Page 60
... Registers MONTR IC EOM CHANL RQST SELECT Am79C30A/32A Data Sheet Mnemonic PPCR1, PPCR2, PPCR 3 PPSR PPIER MTDR MRDR CITDR0, CITDR1 CIRDR0, CIRDR1 PORT PORT IOM 2 MODE MODE ACTV/ SELECT SELECT ...
Page 61
... Monitor Channel Receive Data Available—This bit is set by hardware to indicate that a byte of data has been received on the monitor channel and is available in the Monitor Receive Data Register CHNG MONTR IN IN ABORT C/I 1 C/I 0 RECVD DATA DATA Am79C30A/32A Data Sheet MONTR MONTR MONTR XMIT RECV EOM BUFFR DATA RECVD AVAIL AVAIL ...
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... IN C/I0 ABORT DATA DATA RECVD DATA DATA DATA BIT 5 BIT 4 BIT DATA DATA DATA BIT 5 BIT 4 BIT 3 Am79C30A/32A Data Sheet ENABL ENABL ENABL MONTR MONTR MONTR XMIT RECV EOM BUFFR DATA RECVD AVAIL AVAIL DATA DATA DATA ...
Page 63
... C/I0 DATA RSRVD BIT 3 (MSB C/I1 C/I1 C/I1 DATA DATA DATA BIT 5 BIT 4 BIT 3 (MSB C/I1 C/I C/I1 DATA DATA DATA BIT 5 BIT 4 BIT 3 (MSB) Am79C30A/32A Data Sheet C/I0 C/I0 C/I0 DATA DATA DATA BIT 0 BIT 2 BIT 1 (LSB C/I0 C/I0 C/I0 DATA DATA DATA BIT0 BIT 2 BIT 1 (LSB C/I1 C/I1 C/I1 ...
Page 64
... When in IOM-2 SLAVE mode the received S/G bit is used as the Clear To Send input into the DLC block. TIC Address Bus and Bus Accessed Refer to TIC bus operation section. 2–0 TIC Bus Address—Device address to be used on TIC bus. Default is 111 REV CODE RSRVD RSRVD BIT 0 (LSB) Am79C30A/32A Data Sheet SCLK RSRVD RSRVD INVRT ENABL ...
Page 65
... DSC circuit in place of the IDC circuit. Figure 16 illustrates applications with increased B-channel data processing requirements. Am79C30A DSC Circuit Audio Processor B-Channel PP LIU MUX D-Channel MPI OSC DLC Interrupt Power Reversal Interrupt LCD Display Figure 14. ISDN Telephone Am79C30A/32A Data Sheet Surge S/T Protection Interface Power Controller 5V 09893H-10 65 ...
Page 66
... Microprocessor Interface Interrupts 3 Microcontroller Figure 15. Terminal Adapter (V.110/V.120) With Voice Upgrade Capability 66 Speaker Tone Am79C32A DSC Circuit Serial B-Channel PP Port MUX D-Channel MPI OSC DLC Power Reversal Interrupt MCLK RAM ROM Am79C30A/32A Data Sheet Surge S/T Interface LIU Protection Power Controller 5V 09893H-11 ...
Page 67
... Figure 16. PC Add-On Board ( Data Channels) Analog Telephone Interface Am79C30A DSC Circuit Audio Processor B-Channel LIU PP MUX D-Channel MPI DLC Dual-Port Dual-Port ROM RAM RAM Controller Interface PC Bus Interface PC Bus Am79C30A/32A Data Sheet Surge S/T Protection Optional Program DRAM Memory Controller 09893H-12 67 ...
Page 68
... IOL = 2 µA IOL = 7 µA IOH = –400 µA = –10 µA 0 < VOUT < VCC Output in High-Z State 0 < VIN < VCC Digital Inputs LIN1/LIN2 XTAL2 Temp = 255C Freq = 1 MHz Temp = 255C Freq = 1 MHz Am79C30A/32A Data Sheet Preliminary Unit Min Max ...
Page 69
... AC CHARACTERISTICS ± 5 0° 70° C; MCLK = 3.072 MHz Table 52. MAP Analog Characteristics (Am79C30A only) Parameter Parameter Descriptions Symbol Analog Input Impedence Z IN AINA or AINB to AREF Allowable Offset Voltage at ...
Page 70
... G.714 is by device characterization. Pro- duction testing of individual par ts includes those parameters shown in Table 54. Half-channel parameters are specified from AINA or AINB input pins channel for the transmit path, Table 53. MAP Transmission Characteristics (Am79C30A only) Parameter Symbol Parameter Descriptions Transmit Frequency Response (Attenuation vs. ...
Page 71
... Table 54. Codec Performance Specifications (Am79C30A only) Parameter Parameter Descriptions Symbol TXG Transmit absolute gain RXGE Receive absolute gain at EAR1/EAR2 (nominal) RXGL Receive absolute gain TXSTD Transmit signal/total distortion; CCITT method 2, 1020 Hz (Tx gain = 0) RXSTD Receive signal/total distortion; CITT method 2, 1020 Hz (Rx gain = 0) TXGT Transmit gain tracking ...
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... Figure 17. Attenuation/Frequency Distortion (Transmit) 750 380 130 500 Figure 18. Group Delay Variation with Frequency (Transmit) 72 Frequency (Hz) 600 1000 Frequency (Hz) Am79C30A/32A Data Sheet 9 dB 09893H-13 2600 2800 09893H-14 ...
Page 73
... Input Level (dBm0) –1.6 Figure 19. Gain Tracking Error (Transmit) (CCITT Method 2 at 1020 Hz) Am79C30A/32A Data Sheet –10 +3 09893H-15 73 ...
Page 74
... Figure 20. Signal-to-Total Distortion Ratio (Transmit) (CCITT Method 2 at 1020 Hz) 0.9 0.25 0 –0.25 300 1020 Frequency (Hz) Figure 21. Attenuation/Frequency Distortion (Receive) 74 –45 –40 –30 Input Level (dBm0) Am79C30A/32A Data Sheet –10 0 09893H- 09893H-17 3000 3400 3600 3900 ...
Page 75
... Frequency (Hz) Figure 22. Group Delay Variation with Frequency (Receive) 1.6 0.6 0.3 –55 –50 –40 –0.3 –0.6 Input Level (dBm0) –1.6 Figure 23. Gain Tracking Error (Receive) (CCITT Method 2 at 1020 Hz) Am79C30A/32A Data Sheet 2600 2800 09893H-16 –10 +3 09893H-17 75 ...
Page 76
... Input Level (dBm0) Figure 24. Signal-to-Total-Distortion Ratio (Receive) (CCITT Method 2 at 1020 Hz) 76 –45 –40 –30 Am79C30A/32A Data Sheet –10 0 09893H-18 ...
Page 77
... The 530-mV receive input level is equivalent to 9 attenuation from a nominal transmit level when measured at the LIN pins. Allowing 0.5-dB loss in the isolation transformer, and 1.0-dB loss in the input isolation resistors, this level will guarantee compliance to the CCITT receiver sensitivity spec of 7.5 dB when measured at the S reference point. 3. Typical receiver performance is 220 mV. Am79C30A/32A Data Sheet Preliminary Unit Min ...
Page 78
... Figure 25. System Interface to LIU High Mark 200 09893H- High Mark U a Figure 27. Differential Output Signals Between LOUT2 and LOUT1 (Using the Am79C30A/32A Data Sheet + (s-reference (s-reference) L 09893H-19 LOUT Low Mark c Low Mark ...
Page 79
... DC impedance of the transformer primary (line side of transformer). PRIM the DC impedance of the TE connecting cord; typically 4–6 ohms. CORD the transformer turns ratio ( for Am79C30A/32A the S-interface line impedance (50 ohms the desired load current for the CCITT transmission templates (7.5 mA for 50-ohm line). ...
Page 80
... If CS goes High before WR goes High, the minimum Address Hold time becomes 12 ns and WR pulse width, Address setup and hold, and Data setup and hold timing are measured from the points where both CS and are Low simultaneously. 80 Am79C30A/32A Data Sheet Min Max Units ...
Page 81
... Interrupt Timing Parameter Symbol Parameter Description t INT Cycle Time INTC t INT Recovery Time REC INT t AVWL t WRCS t WLWH Write Read t DSWH t INTC Figure 30. INT Timing Am79C30A/32A Data Sheet t AHWH t WHCH t WHWL Write t DHWH 09893H-21 Min Max Units 125 ms 500 ns t REC 09893H-22 81 ...
Page 82
... Due to clock start-up times, the hookswitch Min and Max Debounce times are approximately 3 ms greater in Power-Down Mode. 4. RESET HSW INT Figure 32. Hookswitch Debounce Timing 82 t PHRL RES t R Figure 31. Reset Timing Am79C30A/32A Data Sheet Min Max Units 1 µs 1 µ µs Min Max Units 16 16. 370 µs t 09893H-23 F ...
Page 83
... MHz 768 kHz 384 kHz 12.288 MHz 6.144 MHz 4.096 MHz 3.072 MHz MCLK Load < 80pF 1.536 MHz 768 kHz 384 kHz t CLCH 0 CLCL Am79C30A/32A Data Sheet Min Max Units 81.374 81.387 Min Max Units ...
Page 84
... RISE 1 PWL PWH t CLK Figure 34. OSC/MCLK Timing Test Conditions SCLK Load < SCLK Load < MCLK Load < SCLK Load < SBOUT/SFS Load = 80 pF Am79C30A/32A Data Sheet 09893H-26 Min Max Units 5.025 5.392 µs 2.594 2.615 µs 2.431 2.777 µs 20 ...
Page 85
... This timing diagram reflects SCLK for PPCR2( For PPCR2( the diagram is identical except that the SCLK waveform should be inverted. Figure 36. SBP Mode MCLK/SCLK/SFS Timing Figure 35. SBP Mode Timing t MCSC t CHFS t CLDO t t DICH Am79C30A/32A Data Sheet Bf 09893H-27 t CHFS t CLDO CHDZ 09893H-28 85 ...
Page 86
... R F SFS t SF SFS t FH SFS t FD SFS t WFH SFS t WFL SBOUT t DSC SBOUT t DHC SBIN t SD SBIN t HD Am79C30A/32A Data Sheet Min Max Units 50 ns 487 815 ns 260 – 100 ...
Page 87
... In Master Mode, SFS is 16 SCLK cycle + setup time + hold time in length. ** Bit 0 Bit 1 Detail BLH BHL SCU WFH t DSC Detail A Figure 37. IOM-2 Timing Am79C30A/32A Data Sheet Bit DHC t HD Transmitter Side Receiver Side t SD 09893H-29 87 ...
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... AC testing inputs are driven at 2.4 V for a logical 1, and 0.45 V for a logical 0. Timing measurements are made at 2.0 V and 0.8 V for a logical 1, and a logical 0, respectively. Figure 38. Switching Test Input/Output Waveform 88 (Input) 2.0 V Test Points 0.8 V Device Under Test C Includes Jig Capacitance L Figure 39. Switching Test Load Circuit Am79C30A/32A Data Sheet 2.0 V 0.8 V 09893H- 09893H-31 ...
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... C1 –36 –36 –36 –36 36 –36 –36 –36 –24 Am79C30A/32A Data Sheet Hex Gain (dB) MSB LSB –36 –35 –35 –35 –35 –35 –35 –35 – ...
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... BB –18 –18 –18 –18 –18 –18 –7 –7 –7 Am79C30A/32A Data Sheet Hex Gain (dB) MSB LSB –18 –18 –18 –17 –17 –17 –17 –17 – ...
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... Am79C30A/32A Data Sheet Hex Gain (dB) MSB LSB –3 –3 –3 –3 –2 –2 –2 –2 –2 – ...
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... Hex Gain (dB) MSB LSB –11 –11 –11 Am79C30A/32A Data Sheet Hex Gain (dB) MSB LSB 10.6 ...
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... BB –7 –7 –7 – Am79C30A/32A Data Sheet Hex Gain (dB) MSB LSB –6 –6 –6 –6 –6 –6 –5 –5 –5 – ...
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... Am79C30A/32A Data Sheet Hex Gain (dB) MSB LSB ...
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... Am79C30A/32A Data Sheet Hex Gain (dB) MSB LSB –inf ...
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... APPENDIX B KEY DESIGN HINTS FOR THE DSC/IDC CIRCUIT Due to the high level of integration of the Am79C30A/ 32A DSC/IDC circuit easy to overlook important design information when reading the data sheet. The following list of key design hints has been compiled to streamline the design process. A comprehensive se- ries of ISDN application notes and tutorials is available from AMD ...
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... GR, GER, STGR, and ATGR), these register blocks should not be accessed more fre- quently than 128-µs intervals. This allows the inter- nal buffers to the map to operate properly, since they are updated only once per frame. Am79C30A/32A Data Sheet 97 ...
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... Pin 1 I.D. .650 .656 .026 .032 TOP VIEW Note: Dimensions are measured in inches. 98 .042 .056 .009 .015 .050 REF Am79C30A/32A Data Sheet .062 .083 .500 .590 REF .630 .013 .021 .090 .120 .165 SEATING PLANE .180 SIDE VIEW ...
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... PHYSICAL DIMENSIONS 1 -A- 0.95 1.05 1.00 REF. Note: Dimensions are measured in inches. PQT 44 44 -D- 9.80 10.20 11.80 12.20 TOP VIEW 11° – 13° 0.80 BSC 11° – 13° 0.30 0.45 SIDE VIEW Am79C30A/32A Data Sheet 11.80 12.20 9.80 -B- 10.20 1.20 MAX 99 ...
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... AMD, the AMD logo and combinations thereof are trademarks of Advanced Micro Devices, Inc. AmMAP, Digital Subscriber Controller, DSC, and IDC are trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 100 Am79C30A/32A Data Sheet ...
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... AMENDMENT Am79C30A/32A Digital Subscriber Controller™ (DSC™) Circuit Table 23: Amplitude Gain Coefficients on page 27 of the Am79C30A/32A final data sheet has the following changes: The tone gain block was intended to provide amplitude steps with a tolerance of approximately 0.5 dB. The following additional codes can also be used: – ...