89hpes24t6g2 Integrated Device Technology, 89hpes24t6g2 Datasheet

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89hpes24t6g2

Manufacturer Part Number
89hpes24t6g2
Description
24-lane, 6-port Gen2 Pcie I/o Expansion Switch
Manufacturer
Integrated Device Technology
Datasheet

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Part Number:
89hpes24t6g2ZCALG
Manufacturer:
IDT
Quantity:
20 000
Device Overview
Express® switching solutions. The PES24T6G2 is a 24-lane, 6-port
Gen2 peripheral chip that performs PCI Express base switching with a
feature set optimized for high performance applications such as servers,
storage, and communications systems. It provides connectivity and
switching functions between a PCI Express upstream port and up to five
downstream ports and supports switching between downstream ports.
Features
Block Diagram
© 2008 Integrated Device Technology, Inc.
The 89HPES24T6G2 is a member of IDT’s PRECISE™ family of PCI
SerDes
Logical
– Twenty-four 5 Gbps Gen2 PCI Express lanes supporting
– Up to six switch ports
– Support for Max Payload Size up to 2048 bytes
– Supports one virtual channel and eight traffic classes
– Fully compliant with PCI Express base specification Revision
– Automatic per port link width negotiation to x8, x4, x2, or x1
– Automatic lane reversal on all ports
– Automatic polarity inversion
– Supports in-band hot-plug presence detect capability
– Supports external signal for hot plug event notification allowing
Layer
High Performance PCI Express Switch
Flexible Architecture with Numerous Configuration Options
Phy
Multiplexer / Demultiplexer
5 Gbps and 2.5 Gbps operation
2.0
SCI/SMI generation for legacy operating systems
Transaction Layer
SerDes
Data Link Layer
Logical
Layer
Phy
(Port 0)
SerDes
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Layer
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Frame Buffer
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IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
®
SerDes
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Layer
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24-Lane 6-Port
Gen2 PCI Express® Switch
*Notice: The information in this document is subject to change without notice
6-Port Switch Core / 24 Gen2 PCI Express Lanes
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
SerDes
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Layer
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(Port 1)
Route Table
Figure 1 Internal Block Diagram
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Layer
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SerDes
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Layer
1 of 51
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Arbitration
– Dynamic link width reconfiguration for power/performance
– Configurable downstream port PCI-to-PCI bridge device
– Crosslink support
– Supports ARI forwarding defined in the Alternative Routing-ID
– Ability to load device configuration from serial EEPROM
– PCI compatible INTx emulation
– Supports bus locked transactions, allowing use of PCI Express
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
– Integrates twenty-four 5 Gbps / 2.5 Gbps embedded SerDes,
– Ability to disable peer-to-peer communications
– Supports ECRC and Advanced Error Reporting
– All internal data and control RAMs are SECDED ECC
– Supports PCI Express hot-plug on all downstream ports
– Supports upstream port hot-plug
Legacy Support
Highly Integrated Solution
Reliability, Availability, and Serviceability (RAS) Features
Port
optimization
numbering
Interpretation (ARI) ECN for virtualized and non-virtualized
environments
with legacy software
queueing
8B/10B encoder/decoder (no separate transceivers needed)
protected
Scheduler
Preliminary Information*
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Layer
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Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
SerDes
89HPES24T6G2
Logical
Layer
Phy
(Port 5)
SerDes
Data Sheet
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May 7, 2008
SerDes
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DSC 6930

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