89hpes24t3g2 Integrated Device Technology, 89hpes24t3g2 Datasheet

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89hpes24t3g2

Manufacturer Part Number
89hpes24t3g2
Description
24-lane, 3-port Gen2 Pcie I/o Expansion Switch
Manufacturer
Integrated Device Technology
Datasheet

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Device Overview
Express® switching solutions. The PES24T3G2 is a 24-lane, 3-port
Gen2 peripheral chip that performs PCI Express base switching with a
feature set optimized for high performance applications such as servers,
storage, and communications systems. It provides connectivity and
switching functions between a PCI Express upstream port and two
downstream ports and supports switching between downstream ports.
Features
Block Diagram
© 2008 Integrated Device Technology, Inc.
The 89HPES24T3G2 is a member of IDT’s PRECISE™ family of PCI
High Performance PCI Express Switch
– Twenty-four 5 Gbps Gen2 PCI Express lanes supporting
– Up to three switch ports
– Support for Max Payload Size up to 2048 bytes
– Supports one virtual channel and eight traffic classes
– Fully compliant with PCI Express base specification Revision
Flexible Architecture with Numerous Configuration Options
– Automatic per port link width negotiation to x8, x4, x2, or x1
– Automatic lane reversal on all ports
– Automatic polarity inversion
– Supports in-band hot-plug presence detect capability
– Supports external signal for hot plug event notification allowing
5 Gbps and 2.5 Gbps operation
2.0
SCI/SMI generation for legacy operating systems
SerDes
Logical
Layer
Phy
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
SerDes
Logical
Layer
Phy
Frame Buffer
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
...
®
SerDes
Logical
Layer
Phy
24-Lane 3-Port
Gen2 PCI Express® Switch
*Notice: The information in this document is subject to change without notice
3-Port Switch Core / 24 Gen2 PCI Express Lanes
Route Table
SerDes
Logical
Figure 1 Internal Block Diagram
Layer
Phy
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
SerDes
Logical
Layer
Phy
1 of 49
...
Arbitration
– Dynamic link width reconfiguration for power/performance
– Configurable downstream port PCI-to-PCI bridge device
– Crosslink support
– Supports ARI forwarding defined in the Alternative Routing-ID
– Ability to load device configuration from serial EEPROM
– PCI compatible INTx emulation
– Supports bus locked transactions, allowing use of PCI Express
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
– Integrates twenty-four 5 Gbps / 2.5 Gbps embedded SerDes,
– Ability to disable peer-to-peer communications
– Supports ECRC and Advanced Error Reporting
– All internal data and control RAMs are SECDED ECC
– Supports PCI Express hot-plug on all downstream ports
– Supports upstream port hot-plug
SerDes
Legacy Support
Highly Integrated Solution
Reliability, Availability, and Serviceability (RAS) Features
Logical
Layer
Port
Phy
optimization
numbering
Interpretation (ARI) ECN for virtualized and non-virtualized
environments
with legacy software
queueing
8B/10B encoder/decoder (no separate transceivers needed)
protected
SerDes
Logical
Layer
Phy
Multiplexer / Demultiplexer
Scheduler
Transaction Layer
Preliminary Information*
Data Link Layer
SerDes
Logical
Layer
Phy
89HPES24T3G2
...
SerDes
Logical
Data Sheet
Layer
Phy
May 7, 2008
DSC 6930

Related parts for 89hpes24t3g2

89hpes24t3g2 Summary of contents

Page 1

... Device Overview The 89HPES24T3G2 is a member of IDT’s PRECISE™ family of PCI Express® switching solutions. The PES24T3G2 is a 24-lane, 3-port Gen2 peripheral chip that performs PCI Express base switching with a feature set optimized for high performance applications such as servers, storage, and communications systems ...

Page 2

... IDT 89HPES24T3G2 Data Sheet – Hot-swap capable I/O – External Serial EEPROM contents are checksum protected – Supports PCI Express Device Serial Number Capability – Capability to monitor link reliability and autonomously change link speed to prevent link instability ◆ Power Management – Utilizes advanced low-power design techniques to achieve low typical power consumption – ...

Page 3

... IDT 89HPES24T3G2 Data Sheet Table 1 Master and Slave SMBus Address Assignment for 27x27mm Package As shown in Figure 3, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure 3(a), the master and slave SMBuses are tied together and the PES24T3G2 acts both as a SMBus master as well as a SMBus slave on this bus. This requires that the SMBus master or processor that has access to PES24T3G2 registers supports SMBus arbitration ...

Page 4

... IDT 89HPES24T3G2 Data Sheet Pin Description The following tables list the functions of the pins provided on the PES24T3G2. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level ...

Page 5

... IDT 89HPES24T3G2 Data Sheet Signal SSMBDAT 1. MSMBADDR pins are not available in the 19mm package. Address hardwired to 0x50. 2. SSMBADDR pins are not available in the 19mm package. Address hardwired to 0x77. Signal GPIO[0] GPIO[1] GPIO[2] 1 GPIO[3] 1 GPIO[4] 1 GPIO[5] 1 GPIO[6] GPIO[7] GPIO[8] GPIO[9] GPIO[10] 1. GPIO pins are not available in the 19mm package. ...

Page 6

... IDT 89HPES24T3G2 Data Sheet Signal CCLKDS CCLKUS 1 MSMBSMODE PERSTN 2 RSTHALT SWMODE[2:0] 1. MSMBSMODE is not available in the 19mm package, resulting in the master SMBus operating only at 400 KHz. 2. RSTHALT is not available in the 19mm package. Signal JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS Type Name/Description I Common Clock Downstream. The assertion of this pin indicates that all downstream ports are using the same clock source as that provided to downstream devices ...

Page 7

... IDT 89HPES24T3G2 Data Sheet Signal JTAG_TRST_N Signal REFRES0, REFRES1 REFRES2, REFRES3 REFRES4, REFRES5 V CORE PEA DD V PEHA DD V PETA Type Name/Description I JTAG Reset. This active low signal asynchronously resets the boundary scan logic and JTAG TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal ...

Page 8

... IDT 89HPES24T3G2 Data Sheet Pin Characteristics Note: Some input pads of the PES24T3G2 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption ...

Page 9

... IDT 89HPES24T3G2 Data Sheet Function SerDes Reference REFRES0 Resistors REFRES1 REFRES2 REFRES3 REFRES4 REFRES5 1. Internal resistor values under typical operating conditions are 92K Ω for pull-up and 90K Ω for pull-down. 2. REFCLKM pin is not available in the 19mm package. 3. SMBus address pins are not available in the 19mm package. ...

Page 10

... IDT 89HPES24T3G2 Data Sheet Logic Diagram — PES24T3G2 Reference Clocks Reference Clock Frequency Selection PCI Express Switch SerDes Input Port 0 PCI Express Switch SerDes Input Port 2 PCI Express Switch SerDes Input Port 4 Master SMBus Interface Slave SMBus Interface System Pins Note: The following pins are not available in the 19mm package: REFCLKM, MSMBADDR, SSMBADDR, MSMBSMODE, RSTHALT, GPIO[6:3] ...

Page 11

... IDT 89HPES24T3G2 Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14. Parameter Description Refclk Input reference clock frequency range FREQ T Rising edge rate C-RISE T Falling edge rate C-FALL V Differential input high voltage ...

Page 12

... IDT 89HPES24T3G2 Data Sheet Parameter T Maximum time to transition to a valid Idle after sending TX-IDLE-SET-TO- an Idle ordered set IDLE T Maximum time to transition from valid idle to diff data TX-IDLE-TO-DIFF- DATA T Transmitter data skew between any 2 lanes TX-SKEW T Minimum Instantaneous Lone Pulse Width ...

Page 13

... IDT 89HPES24T3G2 Data Sheet Signal JTAG JTAG_TCK 1 JTAG_TMS , JTAG_TDI JTAG_TDO JTAG_TRST_N 1. The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high rising edge of JTAG_TCK when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state ...

Page 14

... IDT 89HPES24T3G2 Data Sheet Recommended Operating Supply Voltages Symbol V CORE Internal logic supply DD V I/O I/O supply except for SerDes LVPECL/CML PEA PCI Express Analog Power PEHA PCI Express Analog High Power DD V PETA PCI Express Transmitter Analog Voltage DD V Common ground SS 1 ...

Page 15

... IDT 89HPES24T3G2 Data Sheet Power Consumption Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 13 (and also listed below). Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 13 (and also listed below) ...

Page 16

... IDT 89HPES24T3G2 Data Sheet Thermal Considerations — Option A Package This section describes thermal considerations for the PES24T3G2 (19mm that is relevant to the thermal performance of the PES24T3G2 switch. Symbol T J(max) T A(max) θ Effective Thermal Resistance, Junction-to-Ambient JA(effective) θ Thermal Resistance, Junction-to-Board JB θ ...

Page 17

... IDT 89HPES24T3G2 Data Sheet DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 13. Note: See Table 8, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Description Serial Link PCIe Transmit V Differential peak-to-peak output TX-DIFFp-p voltage V Low-Drive Differential Peak to TX-DIFFp-p-LOW ...

Page 18

... IDT 89HPES24T3G2 Data Sheet I/O Type Parameter Description Serial Link PCIe Receive (cont.) V Differential input voltage (peak- RX-DIFFp-p to-peak) RL Receiver Differential Return RX-DIFF Loss RL Receiver Common Mode Return RX-CM Loss Z Differential input impedance RX-DIFF-DC (DC common mode impedance RX--DC Z Powered down input common RX-COMM-DC ...

Page 19

... IDT 89HPES24T3G2 Data Sheet I/O Type Parameter Description Capacitance C IN Leakage Inputs I/O / LEAK W O Pull-ups/downs I/O LEAK WITH Pull-ups/downs 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 2.0. Gen1 Min Typ Max — — 8.5 — — — — — — ...

Page 20

... IDT 89HPES24T3G2 Data Sheet Option A Package Pinout, 19x19mm 324-BGA Signal Pinout The following table lists the pin numbers and signal names for the PES24T3G2 device. Pin Function Alt Pin A1 V B17 I/O B18 I/O C4 ...

Page 21

... IDT 89HPES24T3G2 Data Sheet Pin Function Alt Pin H11 V K13 SS H12 V PEA K14 DD H13 V PEA K15 DD H14 PE4RN04 K16 H15 PE4RP04 K17 H16 V K18 SS H17 PE4TN04 L1 H18 PE4TP04 L2 J1 PE2TP02 L3 J2 PE2TN02 PE2RP02 L6 J5 PE2RN02 PEHA L8 DD ...

Page 22

... IDT 89HPES24T3G2 Data Sheet Pin Function Alt Pin U1 V U10 SS U2 PEREFCLKN U11 U3 V U12 SS U4 PE0TN07 U13 U5 PE0TN06 U14 U6 REFRES1 U15 U7 PE0TN05 U16 U8 PE0TN04 U17 U9 V U18 SS Option A Package Power Pins (19x19mm 324-Pin) V Core V Core G10 D14 G14 ...

Page 23

... IDT 89HPES24T3G2 Data Sheet Option A Package Ground Pins (19x19mm 324-Pin A11 A15 A16 B3 B7 B16 C3 C6 C16 Option A Package Alternate Signal Functions (19x19mm 324-Pin D16 G11 D17 G16 M13 D18 G17 M16 E3 G18 E9 H3 E16 ...

Page 24

... IDT 89HPES24T3G2 Data Sheet Option A Package Signals Listed Alphabetically (19x19mm 324-Pin) Signal Name CCLKDS CCLKUS GPIO_00 GPIO_01 GPIO_02 GPIO_07 GPIO_08 GPIO_09 GPIO_10 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N MSMBCLK MSMBDAT NO CONNECT PE0RN00 PE0RN01 PE0RN02 PE0RN03 PE0RN04 PE0RN05 PE0RN06 PE0RN07 PE0RP00 PE0RP01 PE0RP02 ...

Page 25

... IDT 89HPES24T3G2 Data Sheet Signal Name PE0TN01 PE0TN02 PE0TN03 PE0TN04 PE0TN05 PE0TN06 PE0TN07 PE0TP00 PE0TP01 PE0TP02 PE0TP03 PE0TP04 PE0TP05 PE0TP06 PE0TP07 PE2RN00 PE2RN01 PE2RN02 PE2RN03 PE2RN04 PE2RN05 PE2RN06 PE2RN07 PE2RP00 PE2RP01 PE2RP02 PE2RP03 PE2RP04 PE2RP05 PE2RP06 PE2RP07 PE2TN00 PE2TN01 PE2TN02 PE2TN03 ...

Page 26

... IDT 89HPES24T3G2 Data Sheet Signal Name PE2TN05 PE2TN06 PE2TN07 PE2TP00 PE2TP01 PE2TP02 PE2TP03 PE2TP04 PE2TP05 PE2TP06 PE2TP07 PE4RN00 PE4RN01 PE4RN02 PE4RN03 PE4RN04 PE4RN05 PE4RN06 PE4RN07 PE4RP00 PE4RP01 PE4RP02 PE4RP03 PE4RP04 PE4RP05 PE4RP06 PE4RP07 PE4TN00 PE4TN01 PE4TN02 PE4TN03 PE4TN04 PE4TN05 PE4TN06 PE4TN07 ...

Page 27

... IDT 89HPES24T3G2 Data Sheet Signal Name PE4TP01 PE4TP02 PE4TP03 PE4TP04 PE4TP05 PE4TP06 PE4TP07 PEREFCLKN PEREFCLKP PERSTN REFRES0 REFRES1 REFRES2 REFRES3 REFRES4 REFRES5 SSMBCLK SSMBDAT SWMODE_0 SWMODE_1 SWMODE_2 V CORE PEA PETA Table 23 PES24T3G2 (19x19mm 324-Pin) Alphabetical Signal List (Part ...

Page 28

... IDT 89HPES24T3G2 Data Sheet Option A Package Pinout — Top View Core (Power I/O (Power PETA (Power) ...

Page 29

... IDT 89HPES24T3G2 Data Sheet 19x19mm Package Drawing — 324-Pin AL324/AR324 May 7, 2008 ...

Page 30

... IDT 89HPES24T3G2 Data Sheet 19x19mm Package Drawing — Page Two May 7, 2008 ...

Page 31

... IDT 89HPES24T3G2 Data Sheet Option B Package Pinout, 27x27mm 676-BGA Signal Pinout The following table lists the pin numbers and signal names for the PES24T3G2 device. Pin Function Alt Pin B10 B11 SS A4 JTAG_TDI B12 A5 JTAG_TMS B13 A6 MSMBADDR_1 ...

Page 32

... IDT 89HPES24T3G2 Data Sheet Pin Function Alt Pin F7 V G18 G19 G20 SS F10 V G21 SS F11 V G22 SS F12 NC G23 F13 V G24 SS F14 V G25 SS F15 V G26 SS F16 NC H1 F17 F18 F19 F20 F21 F22 F23 ...

Page 33

... IDT 89HPES24T3G2 Data Sheet Pin Function Alt Pin L25 PE4TP02 N10 L26 PE4TN02 N11 M1 V CORE N12 N13 PEHA N14 PEHA N15 N16 N17 M7 V CORE N18 CORE N19 N20 SS M10 V N21 SS M11 V CORE ...

Page 34

... IDT 89HPES24T3G2 Data Sheet Pin Function Alt Pin U17 U18 U19 V CORE W4 DD U20 V CORE W5 DD U21 U22 PE4RP05 W7 U23 PE4RN05 W8 U24 V PETA W9 DD U25 PE4TP05 W10 U26 PE4TN05 W11 V1 V CORE W12 W13 PEA W14 ...

Page 35

... IDT 89HPES24T3G2 Data Sheet Pin Function Alt Pin AC9 PE0RN06 AD7 AC10 V PEA AD8 DD AC11 PE0RN05 AD9 AC12 V PEHA AD10 DD AC13 PE0RN04 AD11 AC14 V PEHA AD12 DD AC15 PE0RN03 AD13 AC16 V PEA AD14 DD AC17 PE0RN02 AD15 AC18 V PEA AD16 DD AC19 PE0RN01 AD17 ...

Page 36

... IDT 89HPES24T3G2 Data Sheet Option B Package Core Power Pins (27x27mm 676-Pin Package) V Core DD C4 C14 C16 D10 D12 D13 D15 D17 D18 D19 D21 D22 E11 E13 E15 E17 E19 E20 E21 F1 F2 F25 F26 V Core V Core ...

Page 37

... IDT 89HPES24T3G2 Data Sheet Option B Package I/O, PCIe, and Transmitter Power Pins (27x27mm 676-Pin) Table 26 PES24T3G2 (27x27mm 676-Pin) I/O, PCIe, Transmitter Power Pins V I/O V PEA V PEHA B17 F24 H4 B24 K3 H23 C5 K4 H24 K22 M4 C11 K23 M23 C13 K24 ...

Page 38

... IDT 89HPES24T3G2 Data Sheet Option B Package Ground Pins (27x27mm 676-Pin A14 E4 A23 E5 A25 E8 A26 E10 B1 E12 B2 E14 B13 E16 B16 E18 B25 E22 B26 E23 C2 E24 C3 E25 C6 E26 C8 F4 C10 F5 C12 F7 C18 F8 C20 F9 C24 F10 C25 ...

Page 39

... IDT 89HPES24T3G2 Data Sheet Option B Package Alternate Signal Functions (27x27mm 676-Pin) Option B Package No Connect Pins (27x27mm 676-Pin) Pin GPIO B18 GPIO[0] A19 GPIO[1] B19 GPIO[2] A20 GPIO[3] B20 GPIO[4] A22 GPIO[7] Table 28 PES24T3G2 (27x27mm 676-Pin) Alternate Signal Functions NC Pins A16 C26 ...

Page 40

... IDT 89HPES24T3G2 Data Sheet Option B Package Signals Listed Alphabetically (27x27mm 676-Pin) Signal Name CCLKDS CCLKUS GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 GPIO_07 GPIO_08 GPIO_09 GPIO_10 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N MSMBADDR_1 MSMBADDR_2 MSMBADDR_3 MSMBADDR_4 MSMBCLK MSMBDAT MSMBSMODE NO CONNECT Table 30 PES24T3G2 (27x27mm 676-Pin) Alphabetical Signal List (Part ...

Page 41

... IDT 89HPES24T3G2 Data Sheet Signal Name PE0RN00 PE0RN01 PE0RN02 PE0RN03 PE0RN04 PE0RN05 PE0RN06 PE0RN07 PE0RP00 PE0RP01 PE0RP02 PE0RP03 PE0RP04 PE0RP05 PE0RP06 PE0RP07 PE0TN00 PE0TN01 PE0TN02 PE0TN03 PE0TN04 PE0TN05 PE0TN06 PE0TN07 PE0TP00 PE0TP01 PE0TP02 PE0TP03 PE0TP04 PE0TP05 PE0TP06 PE0TP07 PE2RN00 PE2RN01 PE2RN02 ...

Page 42

... IDT 89HPES24T3G2 Data Sheet Signal Name PE2RN04 PE2RN05 PE2RN06 PE2RN07 PE2RP00 PE2RP01 PE2RP02 PE2RP03 PE2RP04 PE2RP05 PE2RP06 PE2RP07 PE2TN00 PE2TN01 PE2TN02 PE2TN03 PE2TN04 PE2TN05 PE2TN06 PE2TN07 PE2TP00 PE2TP01 PE2TP02 PE2TP03 PE2TP04 PE2TP05 PE2TP06 PE2TP07 PE4RN00 PE4RN01 PE4RN02 PE4RN03 PE4RN04 PE4RN05 PE4RN06 ...

Page 43

... IDT 89HPES24T3G2 Data Sheet Signal Name PE4RP00 PE4RP01 PE4RP02 PE4RP03 PE4RP04 PE4RP05 PE4RP06 PE4RP07 PE4TN00 PE4TN01 PE4TN02 PE4TN03 PE4TN04 PE4TN05 PE4TN06 PE4TN07 PE4TP00 PE4TP01 PE4TP02 PE4TP03 PE4TP04 PE4TP05 PE4TP06 PE4TP07 PEREFCLKN PEREFCLKP PERSTN REFCLKM REFRES0 REFRES1 REFRES2 REFRES3 REFRES4 REFRES5 RSTHALT ...

Page 44

... IDT 89HPES24T3G2 Data Sheet Signal Name SSMBADDR_1 SSMBADDR_2 SSMBADDR_3 SSMBADDR_5 SSMBCLK SSMBDAT SWMODE_0 SWMODE_1 SWMODE_2 V CORE PEA PETA Table 30 PES24T3G2 (27x27mm 676-Pin) Alphabetical Signal List (Part I/O Type Location B10 I A10 I B11 I/O A11 I/O B12 I B14 ...

Page 45

... IDT 89HPES24T3G2 Data Sheet Option B Package Pinout (27x27mm) — Top View Core (Power I/O (Power) DD Vss (Ground ...

Page 46

... IDT 89HPES24T3G2 Data Sheet 27x27mm Package Drawing — 676-Pin BL676/BR676 May 7, 2008 ...

Page 47

... IDT 89HPES24T3G2 Data Sheet 27x27mm Package Drawing — Page Two May 7, 2008 ...

Page 48

... IDT 89HPES24T3G2 Data Sheet Revision History April 24, 2008: Initial publication of Preliminary data sheet. May 7, 2008: Added new Table 17, Thermal Considerations for Option B Package, and revised thermal values in Table 16. On Ordering Informa- tion page, changed package designations from RoHS to Green and silicon revision to ZB. ...

Page 49

... IDT 89HPES24T3G2 Data Sheet Ordering Information NN A AAA Product Product Operating Device Family Family Voltage Valid Combinations Option A (19x19mm) 89HPES24T3G2ZBAL 324-ball FCBGA package, Commercial Temperature 89HPES24T3G2ZBALG 324-ball Green FCBGA package, Commercial Temperature Option B (27x27mm) 89HPES24T3G2ZBBL 676-ball FCBGA package, Commercial Temperature 89HPES24T3G2ZBBLG ...

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