89hpes16t7 Integrated Device Technology, 89hpes16t7 Datasheet
89hpes16t7
Manufacturer Part Number
89hpes16t7
Description
16-lane, 7-port Pcie I/o Expansion Switch
Manufacturer
Integrated Device Technology
Datasheet
1.89HPES16T7.pdf
(33 pages)
Available stocks
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Part Number
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Company:
Part Number:
89hpes16t7ZHBXG
Manufacturer:
IDT
Quantity:
329
Device Overview
Express switching solutions. The PES16T7 is a 16-lane, 7-port periph-
eral chip that performs PCI Express packet switching with a feature set
optimized for high performance applications such as servers, storage
and communications/networking. It provides connectivity and switching
functions between a PCI Express upstream port and up to six down-
stream ports and supports switching between downstream ports.
Features
Block Diagram
© 2008 Integrated Device Technology, Inc.
The 89HPES16T7 is a member of the IDT PRECISE™ family of PCI
SerDes
Logical
Layer
Phy
High Performance PCI Express Switch
– Sixteen 2.5 Gbps PCI Express lanes
– Seven switch ports
– Upstream port configurable up to x8
– Two downstream ports configurable up to x4, four downstream
– Low-latency cut-through switch architecture
– Support for Max Payload Sizes up to 2048 bytes
– One virtual channel
– Eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
Flexible Architecture with Numerous Configuration Options
– Automatic per port link width negotiation to x8, x4, x2 or x1
– Automatic lane reversal on all ports
– Automatic polarity inversion on all lanes
– Ability to load device configuration from serial EEPROM
Multiplexer / Demultiplexer
ports are x1
Transaction Layer
Data Link Layer
SerDes
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Layer
Phy
(Port 0)
SerDes
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Layer
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SerDes
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Frame Buffer
Layer
Phy
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
®
SerDes
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Layer
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Multiplexer / Demultiplexer
16-Lane 7-Port
PCI Express® Switch
Transaction Layer
Data Link Layer
SerDes
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7-Port Switch Core / 16 PCI Express Lanes
(Port 1)
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Route Table
Figure 1 Internal Block Diagram
SerDes
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1 of 33
SerDes
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Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
SerDes
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Layer
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(Port 6)
Legacy Support
Highly Integrated Solution
Reliability, Availability, and Serviceability (RAS) Features
Power Management
– PCI compatible INTx emulation
– Bus locking
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
– Integrates sixteen 2.5 Gbps embedded SerDes with 8B/10B
– Supports ECRC and Advanced Error Reporting
– Internal end-to-end parity protection on all TLPs ensures data
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
– Compatible with Hot-Plug I/O expanders used on PC and
– Utilizes advanced low-power design techniques to achieve low
– Supports PCI Power Management Interface specification (PCI-
– Unused SerDes are disabled
Arbitration
Port
queueing
encoder/decoder (no separate transceivers needed)
integrity even in systems that do not implement end-to-end
CRC (ECRC)
server motherboards
typical power consumption
PM 1.1)
• Supports device power management states: D0, D3
SerDes
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D3
Layer
Phy
cold
SerDes
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Mux/Demux
Scheduler
(Port 2)
SerDes
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Layer
DLL
Phy
TL
89HPES16T7
Data Sheet
March 25, 2008
Mux/Demux
(Port 5)
SerDes
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Layer
DLL
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TL
hot
and
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