89hpes12t3bg2 Integrated Device Technology, 89hpes12t3bg2 Datasheet
89hpes12t3bg2
Manufacturer Part Number
89hpes12t3bg2
Description
12-lane 3-port Gen2 Pci Express Switch
Manufacturer
Integrated Device Technology
Datasheet
1.89HPES12T3BG2.pdf
(30 pages)
Device Overview
PCI Express® switching solutions. The PES12T3BG2 is a 12-lane, 3-
port Gen2 peripheral chip that performs PCI Express Base switching
with a feature set optimized for high performance applications such as
servers, storage, and communications/networking. It provides connec-
tivity and switching functions between a PCI Express upstream port and
two downstream ports and supports switching between downstream
ports.
Features
Block Diagram
© 2009 Integrated Device Technology, Inc
The 89HPES12T3BG2 is a member of IDT’s PRECISE™ family of
◆
– Twelve 5 Gbps Gen2 PCI Express lanes
– Three switch ports
– Low latency cut-through switch architecture
– Support for Max Payload Size up to 2048 bytes
– One virtual channel
– Eight traffic classes
– PCI Express Base Specification Revision 2.0 compliant
High Performance PCI Express Switch
• One x4 upstream port
• Two x4 downstream ports
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
(Port 0)
SerDes
Logical
Layer
Phy
Frame Buffer
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
®
12-Lane 3-Port
Gen2 PCI Express® Switch
*Notice: The information in this document is subject to change without notice
3-Port Switch Core / 12 PCI Express Lanes
Route Table
Figure 1 Internal Block Diagram
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
(Port 2)
1 of 30
SerDes
Logical
Layer
Phy
◆
◆
◆
◆
Arbitration
– Automatic per port link width negotiation to x4, x2 or x1
– Automatic lane reversal on all ports
– Automatic polarity inversion
– Ability to load device configuration from serial EEPROM
– Range of 0 to 127.5 degrees Celsius
– Three programmable temperature thresholds with over and
– Automatic recording of maximum high or minimum low
– PCI compatible INTx emulation
– Bus locking
– Incorporates on-chip internal memory for packet buffering and
– Integrates twelve 5 Gbps embedded SerDes with 8b/10b
Flexible Architecture with Numerous Configuration Options
On-Die Temperature Sensor
Legacy Support
Highly Integrated Solution
Port
• Receive equalization (RxEQ)
under temperature threshold alarms
temperature
queueing
encoder/decoder (no separate transceivers needed)
Multiplexer / Demultiplexer
Scheduler
Transaction Layer
Data Link Layer
(Port 4)
SerDes
Logical
Layer
Phy
89HPES12T3BG2
Data Sheet
July 1, 2009
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