89hpes32h8 Integrated Device Technology, 89hpes32h8 Datasheet

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89hpes32h8

Manufacturer Part Number
89hpes32h8
Description
32-lane, 8-port Pcie System Interconnect Switch
Manufacturer
Integrated Device Technology
Datasheet

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89hpes32h8ZAALI
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WIZNET
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100
Device Overview
Express® switching solutions. The PES32H8 is a 32-lane, 8-port system
interconnect switch optimized for PCI Express packet switching in high-
performance applications, supporting multiple simultaneous peer-to-
peer traffic flows. Target applications include servers, storage, communi-
cations, and embedded systems.
Features
Block Diagram
© 2008 Integrated Device Technology, Inc.
The 89HPES32H8 is a member of the IDT PRECISE™ family of PCI
High Performance PCI Express Switch
– Eight maximum switch ports
– Thirty-two 2.5 Gbps embedded SerDes
– Delivers 128 Gbps (16 GBps) aggregate switching capacity
– Low-latency cut-through switch architecture
– Support for Max Payload Size up to 2048 bytes
– Supports two virtual channels and eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
• Four main ports each of which consists of eight SerDes
• Each x8 main port can further bifurcate to 2 x4-ports
• Supports pre-emphasis and receive equalization on per-port
basis
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
®
32-Lane 8-Port PCI Express®
System Interconnect Switch
Frame Buffer
Route Table
DL/Transaction Layer
DL/Transaction Layer
Figure 1 Internal Block Diagram
x8/x4/x2/x1
x8/x4/x2/x1
SerDes
SerDes
8-Port Switch Core
1 of 40
DL/Transaction Layer
DL/Transaction Layer
x8/x4/x2/x1
x8/x4/x2/x1
SerDes
SerDes
Flexible Architecture with Numerous Configuration Options
– Port arbitration schemes utilizing round robin algorithms
– Virtual channels arbitration based on priority
– Automatic per port link width negotiation to x8, x4, x2 or x1
– Automatic lane reversal on all ports
– Automatic polarity inversion on all ports
– Supports locked transactions, allowing use with legacy soft-
– Ability to load device configuration from serial EEPROM
– Ability to control device via SMBus
Highly Integrated Solution
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
– Integrates thirty-two 2.5 Gbps embedded full duplex SerDes,
Reliability, Availability, and Serviceability (RAS) Features
– Redundant upstream port failover capability
– Internal end-to-end parity protection on all TLPs ensures data
ware
queueing
8B/10B encoder/decoder (no separate transceivers needed)
integrity even in systems that do not implement end-to-end
CRC (ECRC)
Arbitration
Scheduler
Port
89HPES32H8
Data Sheet
April 16, 2008

Related parts for 89hpes32h8

89hpes32h8 Summary of contents

Page 1

... Device Overview The 89HPES32H8 is a member of the IDT PRECISE™ family of PCI Express® switching solutions. The PES32H8 is a 32-lane, 8-port system interconnect switch optimized for PCI Express packet switching in high- performance applications, supporting multiple simultaneous peer-to- peer traffic flows. Target applications include servers, storage, communi- cations, and embedded systems ...

Page 2

... IDT 89HPES32H8 Data Sheet – Supports optional PCI Express end-to-end CRC checking – Supports optional PCI Express Advanced Error Reporting – Supports PCI Express Hot-Plug • Compatible with Hot-Plug I/O expanders used on PC motherboards – Supports Hot-Swap ◆ Power Management – Supports PCI Power Management Interface specification, Revision 1.1 (PCI-PM) • ...

Page 3

... IDT 89HPES32H8 Data Sheet As shown in Figure 3, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure 3(a), the master and slave SMBuses are tied together and the PES32H8 acts both as a SMBus master as well as a SMBus slave on this bus. This requires that the SMBus master or processor that has access to PES32H8 registers supports SMBus arbitration ...

Page 4

... IDT 89HPES32H8 Data Sheet Pin Description The following tables lists the functions of the pins provided on the PES32H8. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Differ- ential signals end with a suffix “ ...

Page 5

... IDT 89HPES32H8 Data Sheet Signal PE7TP[3:0] PE7TN[3:0] REFCLKM PEREFCLKP[3:0] PEREFCLKN[3:0] Signal MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT Signal GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] Type Name/Description O PCI Express Port 7 Serial Data Transmit. Differential PCI Express transmit pairs for port 7. When port 6 is merged with port 7, these signals become port 6 transmit pairs for lanes 4 through 7 ...

Page 6

... IDT 89HPES32H8 Data Sheet Signal GPIO[6] GPIO[7] GPIO[8] GPIO[9] GPIO[10] GPIO[11] GPIO[12] GPIO[13] GPIO[14] GPIO[15] GPIO[16] GPIO[17] GPIO[18] GPIO[19] Type Name/Description I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P1RSTN Alternate function pin type: Output ...

Page 7

... IDT 89HPES32H8 Data Sheet Signal GPIO[20] GPIO[21] GPIO[22] GPIO[23] GPIO[24] GPIO[25] GPIO[26] GPIO[27] GPIO[28] GPIO[29] GPIO[30] GPIO[31] Type Name/Description I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN0 ...

Page 8

... IDT 89HPES32H8 Data Sheet Signal CCLKDS CCLKUS MSMBSMODE P01MERGEN P23MERGEN P45MERGEN P67MERGEN PERSTN RSTHALT SWMODE[3:0] Type Name/Description I Common Clock Downstream. When the CCLKDS pin is asserted, it indicates that a common clock is being used between the downstream device and the downstream port. I Common Clock Upstream. When the CCLKUS pin is asserted, it indicates that a common clock is being used between the upstream device and the upstream port ...

Page 9

... IDT 89HPES32H8 Data Sheet Signal JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N Signal V CORE APE Type Name/Description I JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle ...

Page 10

... IDT 89HPES32H8 Data Sheet Pin Characteristics Note: Some input pads of the PES32H8 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption ...

Page 11

... IDT 89HPES32H8 Data Sheet Function PCI Express Interface (cont.) SMBus General Purpose I/O System Pins EJTAG / JTAG 1. Schmitt Trigger Input (STI) Pin Name Type Buffer PEREFCLKN[3:0] I LVPECL/ CML PEREFCLKP[3:0] I REFCLKM I LVTTL MSMBADDR[4:1] I LVTTL MSMBCLK I/O MSMBDAT I/O SSMBADDR[5,3:1] I SSMBCLK I/O SSMBDAT I/O GPIO[31:0] I/O LVTTL CCLKDS I LVTTL ...

Page 12

... IDT 89HPES32H8 Data Sheet Logic Diagram — PES32H8 Reference Clocks PCI Express Switch SerDes Input Port 0 PCI Express Switch SerDes Input Port 1 PCI Express Switch SerDes Input Port 2 PCI Express Switch SerDes Input Port 3 PCI Express Switch SerDes Input Port 7 Master ...

Page 13

... IDT 89HPES32H8 Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14. Parameter PEREFCLK Refclk Input reference clock frequency range FREQ 2 Refclk Duty cycle of input clock Rise/Fall time of input clocks Differential input voltage swing ...

Page 14

... IDT 89HPES32H8 Data Sheet 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1 Signal GPIO 1 GPIO[31:0] 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. 2. The values for this symbol were determined by calculation, not by testing. ...

Page 15

... IDT 89HPES32H8 Data Sheet JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO JTAG_TRST_N Recommended Operating Supply Voltages Symbol V CORE Internal logic supply DD V I/O I/O supply except for SerDes LVPECL/CML PCI Express Digital Power DD V APE PCI Express Analog Power PCI Express Serial Data Transmit ...

Page 16

... IDT 89HPES32H8 Data Sheet Recommended Operating Temperature Power Consumption Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 13 (and also listed below). Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 13 (and also listed below) ...

Page 17

... IDT 89HPES32H8 Data Sheet Note important for the reliability of this device in any user environment that the junction temperature not exceed the T specified in Table 16. Consequently, the effective junction to ambient thermal resistance ( maintained below the value determined by the formula: θ )/P JA ...

Page 18

... IDT 89HPES32H8 Data Sheet DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 13. Note: See Table 8, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Serial Link PCIe Transmit V Differential peak-to-peak output voltage TX-DIFFp-p V De-emphasized differential output voltage TX-DE-RATIO V DC Common mode voltage ...

Page 19

... IDT 89HPES32H8 Data Sheet I/O Type Parameter Other I/Os LOW Drive I OL Output I OH High Drive I OL Output I OH Schmitt Trig ger Input V IH (STI) Input Capacitance C IN Leakage Inputs I/O / LEAK W O Pull-ups/downs I/O LEAK WITH Pull-ups/downs 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.0a. ...

Page 20

... IDT 89HPES32H8 Data Sheet Package Pinout — 900-BGA Signal Pinout for PES32H8 The following table lists the pin numbers and signal names for the PES32H8 device. Pin Function Alt Pin GPIO_19 B10 ...

Page 21

... IDT 89HPES32H8 Data Sheet Pin Function Alt Pin E17 PE2RN03 F23 E18 PE2RN02 F24 E19 V F25 SS E20 PE2RN01 F26 E21 PE2RN00 F27 E22 V F28 SS E23 V F29 SS E24 V F30 SS E25 MSMBCLK G1 E26 E27 E28 E29 E30 ...

Page 22

... IDT 89HPES32H8 Data Sheet Pin Function Alt Pin K11 V PE L17 DD K12 V L18 SS K13 V PE L19 DD K14 V L20 SS K15 V PE L21 DD K16 V PE L22 DD K17 V L23 SS K18 V PE L24 DD K19 V L25 SS K20 V PE L26 DD K21 V L27 SS K22 V L28 SS K23 V L29 SS K24 ...

Page 23

... IDT 89HPES32H8 Data Sheet Pin Function Alt Pin R5 PE4RN03 T11 R6 V T12 T13 T14 T15 DD R10 V PE T16 DD R11 V CORE T17 DD R12 V CORE T18 DD R13 V T19 SS R14 V CORE T20 DD R15 V T21 SS R16 V CORE T22 DD R17 ...

Page 24

... IDT 89HPES32H8 Data Sheet Pin Function Alt Pin W29 PE0TN01 AA5 W30 PE0TP01 AA6 Y1 PE5TP02 AA7 Y2 PE5TN02 AA8 Y3 V AA9 SS Y4 PE5RP02 AA10 Y5 PE5RN02 AA11 Y6 V AA12 AA13 AA14 AA15 DD Y10 V PE AA16 DD Y11 V CORE AA17 ...

Page 25

... IDT 89HPES32H8 Data Sheet Pin Function Alt Pin AD23 V AE29 SS AD24 GPIO_09 1 AE30 AD25 V AF1 SS AD26 V AF2 SS AD27 V AF3 SS AD28 V AF4 SS AD29 V AF5 SS AD30 V AF6 SS AE1 V AF7 SS AE2 V AF8 SS AE3 V AF9 SS AE4 V AF10 SS AE5 CCLKUS AF11 AE6 V IO AF12 DD AE7 V AF13 ...

Page 26

... IDT 89HPES32H8 Data Sheet Pin Function Alt Pin AJ17 PE7TN01 AJ28 AJ18 V AJ29 SS AJ19 PE7TN02 AJ30 AJ20 PE7TN03 AK1 AJ21 V AK2 SS AJ22 V AK3 SS AJ23 V AK4 SS AJ24 V AK5 SS AJ25 V AK6 SS AJ26 V AK7 SS AJ27 GPIO_01 AK8 Alternate Signal Functions Pin AH28 GPIO_05 AC23 ...

Page 27

... IDT 89HPES32H8 Data Sheet Power Pins V Core V Core DD DD L11 T17 L12 T19 L13 T20 L15 U11 L17 U12 L18 U14 L19 U16 L20 U18 M11 V11 M13 V13 M15 V15 M17 V17 M19 V19 M20 V20 N11 W11 N12 W12 ...

Page 28

... IDT 89HPES32H8 Data Sheet Ground Pins C10 A6 C11 A7 C12 A8 C13 A9 C14 A10 C15 A13 C16 A16 C17 A19 C18 A22 C19 A23 C20 A24 C21 A25 C22 A29 C23 A30 C24 B1 C25 D10 ...

Page 29

... IDT 89HPES32H8 Data Sheet U21 W17 U22 W19 U23 W21 U24 W23 U25 W25 U28 W28 V12 Y15 V14 Y17 V16 Y24 V18 Y25 V24 Y28 V25 AA3 V26 AA6 V27 AA7 V28 AA8 V29 AA9 ...

Page 30

... IDT 89HPES32H8 Data Sheet Signals Listed Alphabetically Signal Name CCLKDS CCLKUS GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 GPIO_07 GPIO_08 GPIO_09 GPIO_10 GPIO_11 GPIO_12 GPIO_13 GPIO_14 GPIO_15 GPIO_16 GPIO_17 GPIO_18 GPIO_19 GPIO_20 GPIO_21 GPIO_22 GPIO_23 GPIO_24 GPIO_25 GPIO_26 GPIO_27 GPIO_28 GPIO_29 ...

Page 31

... IDT 89HPES32H8 Data Sheet Signal Name JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N MSMBADDR_1 MSMBADDR_2 MSMBADDR_3 MSMBADDR_4 MSMBCLK MSMBDAT MSMBSMODE P01MERGEN P23MERGEN P45MERGEN P67MERGEN PE0RN00 PE0RN01 PE0RN02 PE0RN03 PE0RP00 PE0RP01 PE0RP02 PE0RP03 PE0TN00 PE0TN01 PE0TN02 PE0TN03 PE0TP00 PE0TP01 PE0TP02 PE0TP03 PE1RN00 PE1RN01 PE1RN02 ...

Page 32

... IDT 89HPES32H8 Data Sheet Signal Name PE1RN03 PE1RP00 PE1RP01 PE1RP02 PE1RP03 PE1TN00 PE1TN01 PE1TN02 PE1TN03 PE1TP00 PE1TP01 PE1TP02 PE1TP03 PE2RN00 PE2RN01 PE2RN02 PE2RN03 PE2RP00 PE2RP01 PE2RP02 PE2RP03 PE2TN00 PE2TN01 PE2TN02 PE2TN03 PE2TP00 PE2TP01 PE2TP02 PE2TP03 PE3RN00 PE3RN01 PE3RN02 PE3RN03 PE3RP00 PE3RP01 ...

Page 33

... IDT 89HPES32H8 Data Sheet Signal Name PE3RP03 PE3TN00 PE3TN01 PE3TN02 PE3TN03 PE3TP00 PE3TP01 PE3TP02 PE3TP03 PE4RN00 PE4RN01 PE4RN02 PE4RN03 PE4RP00 PE4RP01 PE4RP02 PE4RP03 PE4TN00 PE4TN01 PE4TN02 PE4TN03 PE4TP00 PE4TP01 PE4TP02 PE4TP03 PE5RN00 PE5RN01 PE5RN02 PE5RN03 PE5RP00 PE5RP01 PE5RP02 PE5RP03 PE5TN00 PE5TN01 ...

Page 34

... IDT 89HPES32H8 Data Sheet Signal Name PE5TN03 PE5TP00 PE5TP01 PE5TP02 PE5TP03 PE6RN00 PE6RN01 PE6RN02 PE6RN03 PE6RP00 PE6RP01 PE6RP02 PE6RP03 PE6TN00 PE6TN01 PE6TN02 PE6TN03 PE6TP00 PE6TP01 PE6TP02 PE6TP03 PE7RN00 PE7RN01 PE7RN02 PE7RN03 PE7RP00 PE7RP01 PE7RP02 PE7RP03 PE7TN00 PE7TN01 PE7TN02 PE7TN03 PE7TP00 PE7TP01 ...

Page 35

... IDT 89HPES32H8 Data Sheet Signal Name PE7TP03 PEREFCLKN0 PEREFCLKN1 PEREFCLKN2 PEREFCLKN3 PEREFCLKP0 PEREFCLKP1 PEREFCLKP2 PEREFCLKP3 PERSTN REFCLKM RSTHALT SSMBADDR_1 SSMBADDR_2 SSMBADDR_3 SSMBADDR_5 SSMBCLK SSMBDAT SWMODE_0 SWMODE_1 SWMODE_2 SWMODE_3 V CORE APE I/O Type Location O AK20 I AB26 I D9 ...

Page 36

... IDT 89HPES32H8 Data Sheet PES32H8 Pinout — Top View Core (Power I/O (Power ...

Page 37

... IDT 89HPES32H8 Data Sheet PES32H8 Package Drawing — 900-Pin AL900/AR900 April 16, 2008 ...

Page 38

... IDT 89HPES32H8 Data Sheet PES32H8 Package Drawing — Page Two April 16, 2008 ...

Page 39

... IDT 89HPES32H8 Data Sheet Revision History July 19, 2007: Initial publication of data sheet. November 14, 2007: Added new parameter, Termination Resistor, to Table 9, Input Clock Requirements. March 28, 2008: Added Thermal Considerations section. April 16, 2008: In Table 16, Thermal Specifications, revised values for θ , θ , and θ ...

Page 40

... IDT 89HPES32H8 Data Sheet Ordering Information A AAA NN Product Operating Device Family Voltage Family Valid Combinations 89HPES32H8ZAAL 900-ball FCBGA package, Commercial Temperature 89HPES32H8ZAAR 900-ball RoHS FCBGA package, Commercial Temperature 89HPES32H8ZAALI 900-ball FCBGA package, Industrial Temperature 89HPES32H8ZAARI 900-ball RoHS FCBGA package, Industrial Temperature ...

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