89hpes3t3 Integrated Device Technology, 89hpes3t3 Datasheet

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89hpes3t3

Manufacturer Part Number
89hpes3t3
Description
3-lane, 3-port Pcie I/o Expansion Switch
Manufacturer
Integrated Device Technology
Datasheet
Device Overview
Express switching solutions. The PES3T3 is a 3-lane, 3-port peripheral
chip that performs PCI Express Base switching. It provides connectivity
and switching functions between a PCI Express upstream port and up to
four downstream ports and supports switching between downstream
ports.
Features
Block Diagram
© 2008 Integrated Device Technology, Inc.
The 89HPES3T3 is a member of IDT’s PRECISE™ family of PCI
High Performance PCI Express Switch
Flexible Architecture with Numerous Configuration Options
Legacy Support
– Three 2.5Gbps PCI Express lanes
– Three switch ports
– x1 Upstream port
– Two x1 Downstream ports
– Low latency cut-through switch architecture
– Support for Max payload sizes up to 256 bytes
– One virtual channel
– Eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
– Automatic lane reversal on all ports
– Automatic polarity inversion on all lanes
– Ability to load device configuration from serial EEPROM
– PCI compatible INTx emulation
– Bus locking
Frame Buffer
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
Transaction Layer
Data Link Layer
Mux / Demux
(Port 0)
SerDes
Logical
®
Layer
Phy
3-Lane 3-Port
PCI Express® Switch
3-Port Switch Core / 3 PCI Express Lanes
Route Table
Figure 1 Internal Block Diagram
Transaction Layer
Data Link Layer
1 of 32
Mux / Demux
(Port 2)
SerDes
Logical
Layer
Phy
Highly Integrated Solution
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
– Integrates three 2.5 Gbps embedded SerDes with 8B/10B
Reliability, Availability, and Serviceability (RAS) Features
– Internal end-to-end parity protection on all TLPs ensures data
– Supports ECRC and Advanced Error Reporting
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
– Compatible with Hot-Plug I/O expanders used on PC mother-
Power Management
– Utilizes advanced low-power design techniques to achieve low
– Supports PCI Power Management Interface specification (PCI-
– Unused SerDes are disabled.
– Supports Advanced Configuration and Power Interface Speci-
Testability and Debug Features
– Built in Pseudo-Random Bit Stream (PRBS) generator
– Numerous SerDes test modes
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
Arbitration
Port
queueing
encoder/decoder (no separate transceivers needed)
integrity even in systems that do not implement end-to-end
CRC (ECRC)
boards
typical power consumption
PM 1.2)
fication, Revision 2.0 (ACPI) supporting active link state
Transaction Layer
Data Link Layer
Mux / Demux
(Port 3)
SerDes
Logical
Layer
Phy
Scheduler
89HPES3T3
Data Sheet
March 31, 2008

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89hpes3t3 Summary of contents

Page 1

... Device Overview The 89HPES3T3 is a member of IDT’s PRECISE™ family of PCI Express switching solutions. The PES3T3 is a 3-lane, 3-port peripheral chip that performs PCI Express Base switching. It provides connectivity and switching functions between a PCI Express upstream port and up to four downstream ports and supports switching between downstream ports ...

Page 2

... IDT 89HPES3T3 Data Sheet ◆ Five General Purpose Input/Output Pins – Each pin may be individually configured as an input or output – Each pin may be individually configured as an interrupt input – Four pins have selectable alternate functions ◆ Option A Package: 13mm x 13mm 144-ball BGA with 1mm ball spacing ◆ ...

Page 3

... IDT 89HPES3T3 Data Sheet General Purpose Input/Output The PES3T3 provides 5 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin may be configured independently as an input or output through software control, and each GPIO pin is shared with another on-chip function. These alter- nate functions may be enabled via software or serial configuration EEPROM ...

Page 4

... IDT 89HPES3T3 Data Sheet Signal GPIO[0] GPIO[1] GPIO[2] GPIO[7] GPIO[9] Signal APWRDISN CCLKDS CCLKUS PERSTN Type Name/Description I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 2 I/O General Purpose I/O ...

Page 5

... IDT 89HPES3T3 Data Sheet Signal RSTHALT SWMODE[2:0] WAKEN Signal JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N Signal V CORE APE Type Name/Description I Reset Halt. When this signal is asserted during a PCI Express fundamental reset, the PES3T3 executes the reset procedure and remains in a reset state with the Master SMBus active ...

Page 6

... IDT 89HPES3T3 Data Sheet Pin Characteristics Note: Some input pads of the PES3T3 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption ...

Page 7

... IDT 89HPES3T3 Data Sheet Logic Diagram — PES3T3 Reference Clocks PCI Express Switch SerDes Input Port 0 PCI Express Switch SerDes Input Port 2 PCI Express Switch SerDes Input Port 3 Master SMBus Interface System Pins PEREFCLKP PEREFCLKN PE0RP[0] PE0RN[0] PE2RP[0] PE2RN[0] PES3T3 PE3RP[0] ...

Page 8

... IDT 89HPES3T3 Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 12 and 13. Parameter PEREFCLK Refclk Input reference clock frequency range FREQ 1 Refclk Duty cycle of input clock Rise/Fall time of input clocks Differential input voltage swing ...

Page 9

... IDT 89HPES3T3 Data Sheet Signal GPIO GPIO[9,7,2:0] 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. 2. The values for this symbol were determined by calculation, not by testing. GPIO (synchronous output) GPIO (asynchronous input) ...

Page 10

... IDT 89HPES3T3 Data Sheet JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO JTAG_TRST_N Recommended Operating Supply Voltages Symbol V CORE Internal logic supply DD V I/O I/O supply except for SerDes LVPECL/CML PCI Express Digital Power DD V APE PCI Express Analog Power PCI Express Serial Data Transmit ...

Page 11

... IDT 89HPES3T3 Data Sheet Recommended Operating Temperature Power Consumption Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 12. Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 12 ...

Page 12

... IDT 89HPES3T3 Data Sheet Thermal Considerations — Option B Package This section describes thermal considerations for the PES3T3 (10mm relevant to the thermal performance of the PES3T3 switch. Symbol T J(max) T A(max) θ Effective Thermal Resistance, Junction-to-Ambient JA(effective) θ Thermal Resistance, Junction-to-Board JB θ ...

Page 13

... IDT 89HPES3T3 Data Sheet DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 12. Note: See Table 7, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Serial Link PCIe Transmit V Differential peak-to-peak output voltage TX-DIFFp-p V De-emphasized differential output voltage TX-DE-RATIO V DC Common mode voltage ...

Page 14

... IDT 89HPES3T3 Data Sheet I/O Type Parameter Other I/Os LOW Drive I OL Output I OH High Drive I OL Output I OH Schmitt Trig ger Input V IH (STI) Input Capacitance C IN Leakage Inputs I/O / LEAK W O Pull-ups/downs I/O LEAK WITH Pull-ups/downs 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1. ...

Page 15

... IDT 89HPES3T3 Data Sheet — 144-BGA Signal Pinout for PES3T3 Option A Package The following table lists the pin numbers and signal names for the PES3T3 device. Pin Function Alt Pin A1 V C11 C12 DD A3 APWRDISN ...

Page 16

... IDT 89HPES3T3 Data Sheet Pin Function Alt Pin M5 PE3TP00 Option A Package — Alternate Signal Functions Option A Package — Power Pins V Core C11 E10 Function Alt Pin PE3RP00 M9 V APE M10 DD Table 18 PES3T3 (13x13, 144-pin) Signal Pin-Out (Part ...

Page 17

... IDT 89HPES3T3 Data Sheet Option A Package — Ground Pins V A1 A12 B11 B12 C10 C12 Option A Package — Signals Listed Alphabetically Signal Name APWRDISN CCLKDS CCLKUS GPIO_00 GPIO_01 GPIO_02 GPIO_07 GPIO_09 JTAG_TCK JTAG_TDI JTAG_TDO JTAG-TMS JTAG-TRST_N MSMBCLK MSMBDAT ...

Page 18

... IDT 89HPES3T3 Data Sheet Signal Name No Connection PE0RN00 PE0RP00 PE0TN00 PE0TP00 PE2RN00 PE2RP00 PE2TN00 PE2TP00 PE3RN00 PE3RP00 PE3TN00 PE3TP00 PEREFCLKN PEREFCLKP PERSTN RSTHALT SWMODE_0 SWMODE_1 SWMODE_2 WAKEN V CORE APE Table 22 89PES3T3 (13x13, 144-pin) Alphabetical Signal List (Part ...

Page 19

... IDT 89HPES3T3 Data Sheet Option A Package Pinout — Top View Core (Power I/O (Power (Power (Power APE (Power ...

Page 20

... IDT 89HPES3T3 Data Sheet Option A Package Drawing — 144-Pin BC144/BCG144 March 31, 2008 ...

Page 21

... IDT 89HPES3T3 Data Sheet Option A Package Drawing — Page Two March 31, 2008 ...

Page 22

... IDT 89HPES3T3 Data Sheet Package B Package Pinout — 132-BGA Signal Pinout for PES3T3 The following table lists the pin numbers and signal names for the PES3T3 132-pin device. Pin Function Alt Pin A1 NC A34 A2 NC A35 A3 V I/O A36 I/O A37 DD A5 ...

Page 23

... IDT 89HPES3T3 Data Sheet Package B Alternate Signal Functions Package B Power Pins V Core A21 A34 A40 A41 A52 A68 Pin GPIO A50 GPIO_00 A49 GPIO_01 A48 GPIO_02 A42 GPIO_07 A39 GPIO_09 Table 24 PES3T3 (10x10, 132-pin) Alternate Signal Functions Core ...

Page 24

... IDT 89HPES3T3 Data Sheet Package B Ground Pins V A9 A43 A46 Package B No Connection Pins B11 B13 B15 B18 B22 Table 26 PES3T3 (10x10, 132-pin) Ground Pins A17 A18 A19 A20 A30 A31 A32 A33 Table 27 PES3T3 (10x10, 132-pin) No Connection Pins ...

Page 25

... IDT 89HPES3T3 Data Sheet Package B Pin Signals Listed Alphabetically Signal Name APWRDISN CCLKDS CCLKUS GPIO_00 GPIO_01 GPIO_02 GPIO_05 GPIO_06 GPIO_07 GPIO_09 JTAG_TCK JTAG_TDI JTAG_TDO JTAG-TMS JTAG-TRST_N MSMBCLK MSMBDAT NC PE0RN00 PE0RP00 PE0TN00 PE0TP00 PE2RN00 PE2RP00 PE2TN00 PE2TP00 PE3RN00 PE3RP00 PE3TN00 PE3TP00 PEREFCLKN ...

Page 26

... IDT 89HPES3T3 Data Sheet Signal Name PERSTN RSTHALT SWMODE_0 SWMODE_1 SWMODE_2 WAKEN V CORE APE Table 28 89PES3T3 (10x10, 132-pin) Alphabetical Signal List (Part I/O Type Location I B45 I B44 I A58 I A57 I B46 I/O A70 See Table 25 for a listing of power pins. ...

Page 27

... IDT 89HPES3T3 Data Sheet Package B Pinout — Top View A72 B1 A71 B60 B59 A70 B58 A69 A68 B57 A67 B56 A66 B55 A65 B54 X A64 B53 B52 A63 B51 A62 A61 B50 A60 B49 A59 B48 A58 B47 A57 B46 ...

Page 28

... IDT 89HPES3T3 Data Sheet Package B Package Drawing — 132-Pin NQ132/NQG132 March 31, 2008 ...

Page 29

... IDT 89HPES3T3 Data Sheet Package B Package Drawing — Page Two Note: Thermal pad size is 6.5mm SQ, as shown in Package Drawing — Page 3 on the next page March 31, 2008 ...

Page 30

... IDT 89HPES3T3 Data Sheet Package B Package Drawing — Page Three March 31, 2008 ...

Page 31

... IDT 89HPES3T3 Data Sheet Revision History March 31, 2008: Publication of final data sheet March 31, 2008 ...

Page 32

... IDT 89HPES3T3 Data Sheet Ordering Information A AAA NN Product Operating Device Family Family Voltage Valid Combinations Option A Package 89HPES3T3ZBBC 144-pin BC144 package, Commercial Temperature 89HPES3T3ZBBCG 144-pin Green BC144 package, Commercial Temperature Option B Package 89HPES3T3ZBNQ 132-pin NQ132 package, Commercial Temperature 89HPES3T3ZBNQG 132-pin Green NQ132 package, Commercial Temperature ...

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