89hpes34h16 Integrated Device Technology, 89hpes34h16 Datasheet

89hpes34h16

Manufacturer Part Number

89hpes34h16

Description

34-lane, 16-port Pcie System Interconnect Switch

Manufacturer

Integrated Device Technology

Datasheet

1.89HPES34H16.pdf (45 pages)

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Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

89hpes34h16ZABL

Manufacturer:

IDT

Quantity:

284

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Device Overview

PCI Express® switching solutions. The PES34H16 is a 34-lane, 16-port

peripheral chip that performs PCI Express packet switching with a

feature set optimized for high-performance applications such as servers,

storage, and communications/networking. It provides connectivity and

switching functions between a PCI Express upstream port and up to

fifteen downstream ports and supports switching between downstream

ports.

Features

Block Diagram

The 89HPES34H16 is a member of the IDT PRECISE™ family of

◆

High Performance PCI Express Switch

– Sixteen maximum switch ports

– Thirty-four 2.5 Gbps embedded SerDes

– Low-latency cut-through switch architecture

– Support for Max Payload Size up to 2048 bytes

– Supports two virtual channels and eight traffic classes

– PCI Express Base Specification Revision 1.1 compliant

• Up to three x8 ports that bifurcate up to six x4 ports

• Ten x1 ports

• Supports pre-emphasis and receive equalization on per-port

basis

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.

DL/Transaction Layer

x8/x4/x2/x1

SerDes

DL/Transaction Layer

34-Lane 16-Port

PCI Express® Switch

*Notice: The information in this document is subject to change without notice

Frame Buffer

x8/x4/x2/x1

Route Table

SerDes

DL/Transaction Layer

Figure 1 Internal Block Diagram

Up to 6 x4 ports and 10 x1 Ports

SerDes

34 PCI Express Lanes

16-Port Switch Core

DL/Transaction Layer

1 of 45

x8/x4/x2/x1

SerDes

. . . . . . .

◆

Flexible Architecture with Numerous Configuration Options

– Port arbitration schemes utilizing round robin algorithms

– Automatic per port link width negotiation from x8 to x4 to x2 or

– Automatic lane reversal on all ports

– Automatic polarity inversion on all lanes

– Supports locked transactions, allowing use with legacy soft-

– Ability to load device configuration from serial EEPROM

– Ability to control device via SMBus

Highly Integrated Solution

– Requires no external components

– Incorporates on-chip internal memory for packet buffering and

– Integrates thirty-four 2.5 Gbps embedded full duplex SerDes,

Reliability, Availability, and Serviceability (RAS) Features

– Redundant upstream port failover capability

– Supports optional PCI Express end-to-end CRC checking

(10)

ware

queueing

8B/10B encoder/decoder (no separate transceivers needed)

DL/Transaction Layer

x8/x4/x2/x1

SerDes

Arbitration

Scheduler

Port

DL/Transaction Layer

SerDes

Preliminary Information*

89HPES34H16

Data Sheet

April 16, 2008

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