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... S71PL512ND0 MirrorBit™ Flash Family Two S29PL256N Devices ( 16-Bit) CMOS 3.0-Volt only Simultaneous Read/Write, Page-Mode Flash Memory Data Sheet Notice to Readers: This document indicates states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that a product qualification has been completed, and that initial production has begun ...
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... However, typographical or specification corrections, or modifications to the valid combinations offered may occur.” Questions regarding these document designations may be directed to your local AMD or Fujitsu sales office S71PL512ND0 MirrorBit™ Flash Family range. Changes IO S71PL512ND0_00_A2 December 6, 2005 ...
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... Page-Mode Flash Memory Data Sheet General Description This document contains information for the S71PL512ND0 MirrorBit MCP product. Refer to the S29PL-N_M0, Rev A2 (S29PL256N/129N/127N) data sheet (included in this document) for full electrical specifications for the Flash memory component. Refer to the PSRAM_15, Rev A2 (PSRAM Type 2), data sheet (included in this document) for full electrical specifications for the pSRAM component ...
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... Power-Up Write Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11 Power Conservation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.1 Standby Mode 11.2 Automatic Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.3 Hardware RESET# Input Operation 11.4 Output Disable (OE Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 S71PL512ND0 MirrorBit™ Flash Family S71PL512ND0_00_A2 December 6, 2005 ...
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... Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 27.1 Read Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 27.2 Write Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 28 pSRAM Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 28.1 Revision A0 (February 16, 2004 28.2 Revision A1 (June 11, 2004 28.3 Revision A2 (February 3, 2005 MCP Revision Summary .88 December 6, 2005 S71PL512ND0_00_A2 S71PL512ND0 MirrorBit™ Flash Family 3 ...
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... Table 13.1 Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 15.1 Memory Array Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 15.2 Sector Protection Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 15.3 CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 15.4 System Interface String Table 15.5 Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 15.6 Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S71PL512ND0 MirrorBit™ Flash Family S71PL512ND0_00_A2 December 6, 2005 ...
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... Timing Waveform of Page Cycle (Page Mode Only).................................................................................84 Figure 27.4. Write Cycle #1 (WE# Controlled) ........................................................................................................85 Figure 27.5. Write Cycle #2 (CS1# Controlled) .......................................................................................................85 Figure 27.6. Timing Waveform of Write Cycle(3) (CS2 Controlled) .............................................................................86 Figure 27.7. Timing Waveform of Write Cycle(4) (UB#, LB# Controlled) .....................................................................86 December 6, 2005 S71PL512ND0_00_A2 S71PL512ND0 MirrorBit™ Flash Family 5 ...
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... Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. S71PL512ND0 MirrorBit™ Flash Family Package Type (Note 2) pSRAM Type FEB084 8.0x11.6 mm Type 2 84-ball MCP-Compatible (FBGA) Valid Combinations S71PL512ND0_00_A2 December 6, 2005 ...
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... Flash 3.0 volt-only single power supply (see Product Selctor Guide for speed options and voltage supply tolerances) pSRAM Power Supply Device ground (common) Pin Not Connected Internally 24 A23–A0 F1-CE# DQ15–DQ0 F2-CE# R-CE1# R Y/BY# R-CE2 OE# WE# WP #/ACC RES ET# UB# LB# S71PL512ND0 MirrorBit™ Flash Family Description 16 7 ...
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... Shared Address OE# WE# F2-CE# CE#s UB#s LB#s CE2 Notes: 1. RY/BY open drain output A23. MAX Flash Flash 2 V CCS V CC pSRAM/SRAM IO - CE# UB# LB# S71PL512ND0 MirrorBit™ Flash Family RY/BY S71PL512ND0_00_A2 December 6, 2005 ...
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... F-V CC R-V CC DQ12 RFU DQ8 DQ2 DQ11 RFU DQ5 RFU RFU RFU F-V CC RFU RFU S71PL512ND0 MirrorBit™ Flash Family A10 Legend NC/DNU All Shared RFU RFU A11 RFU pSRAM Only A12 A15 Flash ...
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... INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. S71PL512ND0 MirrorBit™ Flash Family PIN A1 7 CORNER SD BOTTOM VIEW 3527 \ 16-038.21 \ 10.26.05 S71PL512ND0_00_A2 December 6, 2005 ...
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S29PL-N MirrorBit™ Flash Family S29PL256N, S29PL127N, S29PL129N, 256/128/128 Mb (16/8 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory Data Sheet General Description The Spansion S29PL-N is the latest generation 3.0-Volt page mode read family fabricated using ...
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Input/Output Descriptions and Logic Symbols Table 5.1 identifies the input and output package connections provided on the device. Symbol Type A – A0 Input max DQ15 – DQ0 I/O CE# Input OE# Input WE# Input V Supply SS NC ...
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Block Diagram RY/BY# (See Note RESET# WE# State Control Command Register CE# OE# V Detector CC A – A3 max A2–A0 Notes: 1. RY/BY open drain output A23 (PL256N), A22 ...
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Additional Resources Visit www.amd.com Application Notes T Using the Operation Status Bits in AMD Devices T Simultaneous Read/Write vs. Erase Suspend/Resume T MirrorBit™ Flash Memory Write Buffer Programming and Page Buffer Read T Design-In Scalable Wireless Solutions with Spansion ...
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Product Overview The S29PLxxxN family consists of 256 and 128 Mb, 3.0 volts-only, simultaneous read/write page-mode read Flash devices that are optimized for wireless designs of today that demand large storage array and rich functionality, while requiring low power ...
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Bank Sector Bank Size Count Note: Ellipses indicate that other addresses in sector range follow the same pattern. Bank Sector Bank Size ...
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Device Operations This section describes the read, program, erase, simultaneous read/write operations, and reset features of the Flash devices. Operations are initiated by writing specific commands or a sequence with specific address and data patterns into the command registers ...
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Operation Read Write Standby Output Disable Reset Temporary Sector Unprotect (High Voltage) Legend Logic Low = Don’t Care Sector Address, A Notes: 1. The sector and sector unprotect functions may also be implemented ...
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The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. All addresses are latched ...
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See Table 15.1 for command sequence details. CE# Description See Note Manufacturer ID Read Cycle 1 Read Cycle 2 Read Cycle 3 Sector Protection Verification Indicator Bit Legend Logic Low = V Note: For ...
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Here is an example of Autoselect mode (getting manufacturer ID Define UINT16 example: typedef unsigned short UINT16; */ UINT16 manuf_id; /* Auto Select Entry */ *((UINT16 *)bank_addr + 0x555) = 0x00AA; /* write unlock cycle 1 */ ...
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Program/Erase Operations These devices are capable of single word or write buffer programming operations which are de- scribed in the following sections. The write buffer programming is recommended over single word programming as it has clear benefits from greater ...
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Software Functions and Sample Code Cycle Unlock Cycle 1 Unlock Cycle 2 Program Setup Program Note: Base = Base Address. The following source code example of using the single word program function. See the Spansion Low Level ...
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Write Buffer Programming Write Buffer Programming allows the system to write a maximum of 32 words in one program- ming operation. This results in a faster effective word programming time than the standard word programming algorithms. The Write Buffer ...
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Use of the write buffer is strongly recommended for programming when multiple words are to be programmed. Write buffer programming is approximately four times faster than programming one word at a time. Note that the Secured Silicon, the CFI functions, ...
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Write Next Word, Decrement wc: PA data , – 1 RESET. Issue Write Buffer Abort Reset Command 9.4.3 Sector Erase The sector erase function erases one or more sectors in the memory array. (See Figure 9.3.) The ...
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Any command other than Sector Erase or Erase Suspend during the time-out period resets that bank to the read mode. The system can monitor DQ3 to determine if the sector erase timer has timed out (see the rising ...
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Write Sector Erase Cycles: Sector Address, Data 30h Poll DQ3. Poll DQ3. DQ3 = 1? DQ3 = 1? Yes Yes Yes Yes PASS. Device returns PASS. Device returns to reading array. to reading array. Notes: 1. ...
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When the Embedded Erase algorithm is complete, that bank returns to the read mode and ad- dresses are no longer latched. The system can determine the status of the erase operation by using DQ7 or DQ6/DQ2. See Any commands written ...
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After an erase-suspended program operation is complete, the bank returns to the erase-suspend- read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. In ...
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The system can also write the Autoselect command sequence when the device is in Program Sus- pend mode. The device allows reading Autoselect codes in the suspended sectors, since the codes are not stored in the memory array. When the ...
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Bypass mode, the full 3-cycle RESET command sequence must be used to reset the device. Re- moving V from the ACC input, upon completion of the embedded program or erase operation, HH returns the device to normal operation. T Sectors ...
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Cycle 1 Program Setup Command 2 Program Command /* Example: Unlock Bypass Program Command */ /* Do while in Unlock Bypass Entry Mode! *((UINT16 *)bank_addr + 0x555) = 0x00A0; *((UINT16 *)pa) /* Poll until done or error done ...
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DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ6 – DQ0 may be still invalid. Valid ...
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Read 1 DQ5=1? NO YES Write Buffer Programming? NO Device BUSY, Re-Poll (Note 1) (Note 4) YES Read3 DQ1=1? NO Read 2 Device BUSY, Re-Poll Read 3 YES Read3 DQ1=1 AND DQ7 ≠ Valid Data? NO Device BUSY, Re-Poll Figure ...
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DQ6: Toggle Bit I . rithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I can be read at any address in the same bank, and is valid after the rising ...
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Alterna- tively, it can choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine ...
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Embedded Program Algorithm Standard Mode Embedded Erase Algorithm Reading within Program Program Suspended Sector Suspend Mode (Note 3) Reading within Non-Program Suspended Sector Erase Erase-Suspend-Read Suspend Mode Erase-Suspend-Program Erase-Suspend- Erase Read Suspend Mode Erase-Suspend-Program BUSY State Write to Buffer ...
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Simultaneous Read/Write The simultaneous read/write feature allows the host system to read data from one bank of mem- ory while programming or erasing another bank of memory. An erase operation may also be suspended to read from or program ...
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Mux A21 – A0 A21 – A0 RESET# State WE# Control CE1# and Command CE2# Register WP#/ACC DQ0 – DQ15 A21 – A0 Mux Figure 9.6 Simultaneous Operation Block Diagram for S29PL129N ...
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Writing Commands/Command Sequences During a write operation, the system must drive CE# and WE viding an address, command, and data. Addresses are latched on the last falling edge of WE# or CE#, while data is latched on ...
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Hardware Reset The RESET# input provides a hardware method of resetting the device to reading array data. When RESET# is driven low for at least a period of t operation in progress, tristates all outputs, and ignores all read/write ...
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bank has entered the Autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode DQ1 goes high during a Write Buffer Programming operation, the system must ...
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Advanced Sector Protection/Unprotection The Advanced Sector Protection/Unprotection feature disables or enables programming or erase operations in any or all sectors and can be implemented through software and/or hardware meth- ods, which are independent of each other. This section describes ...
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Lock Register As shipped from the factory, all devices default to the persistent mode when power is applied, and all sectors are unprotected, unless otherwise chosen through the DYB ordering option (see dering Information). The device programmer or host ...
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Notes 1. Each PPB is individually programmed and all are erased in parallel. 2. Entry command disables reads and writes for the bank selected. 3. Reads within that bank return the PPB status for that sector. 4. Reads from other ...
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Notes 1. No software command sequence unlocks this bit unless the device is in the password pro- tection mode; only a hardware reset or a power-up clears this bit. 2. The PPB Lock Bit must be set (programmed to 0) ...
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Yes PASS. Write Lock Register Exit Command: Address XXXh, Data 90h Address XXXh, Data 00h Device returns to reading array Write Unlock Cycles: Address 555h, Data AAh Address ...
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Advanced Sector Protection Software Examples Unique Device PPB Lock Bit 0 = locked unlocked Any Sector Any Sector Any Sector Any Sector Any Sector Any Sector Any Sector Any Sector Table 10.2 contains all possible combinations of ...
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Write Pulse Glitch Protection Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. 10.7.4 Power-Up Write Inhibit If WE# = CE# = RESET mands on the rising ...
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Power Conservation Modes 11.1 Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed ...
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Secured Silicon Sector Flash Memory Region The Secured Silicon Sector provides an extra Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The Secured Silicon Sector is 256 words in length that consists of ...
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Customer Secured Silicon Sector The Customer Secured Silicon Sector is typically shipped unprotected (DQ6 set to 0), allowing customers to utilize that sector in any manner they choose. If the security feature is not required, the Customer Secured Silicon ...
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Cycle Unlock Cycle 1 Unlock Cycle 2 Entry Cycle Note: Base = Base Address. /* Example: SecSi Sector Entry Command */ *((UINT16 *)base_addr + 0x555) = 0x00AA; *((UINT16 *)base_addr + 0x2AA) = 0x0055; *((UINT16 *)base_addr + 0x555) = 0x0088; Cycle ...
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Electrical Specifications 13.1 Absolute Maximum Ratings Storage Temperature Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Operating Ranges Wireless (W) Devices Ambient Temperature (T Industrial (I) Devices Ambient Temperature (T Supply Voltages V Supply Voltages . . . . . . . . . . . . . . . . . . . . ...
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Switching Waveforms All Inputs and Outputs 13.6 V Power Up CC Parameter t VCS t READ Notes ramp rate must exceed 1 V/400 µ internally connected RESET# CE# ...
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DC Characteristics 13.7.1 DC Characteristics (V (CMOS Compatible) Parameter Parameter Description Symbol I Input Load Current LI I Output Leakage Current Active Read Current (1, 3) CC1 Active Write Current (3) CC2 CC ...
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DC Characteristics (V (CMOS Compatible) Parameter Parameter Description Symbol I Input Load Current LI I Output Leakage Current Active Read Current (1, 2) CC1 Active Write Current (2, 3) CC2 ...
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AC Characteristics 13.8.1 Read Operations Parameter JEDEC Std Read Cycle Time (1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay (5) ELQV CE t Page Access Time PACC ...
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CE# t OE# OEH WE# High-Z Output 13.8.3 Hardware Reset (RESET#) Parameter JEDEC Std. t RESET# Pulse Width RP t Reset High Time Before Read RH Note: Not 100% tested. ...
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Erase/Program Timing Parameter JEDEC Std t t AVAV AVWL AS t ASO t t WLAX AH t AHT t t DVWH WHDX DH t OEPH t t GHWL GHWL t t ELWL CS ...
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Addresses CE# OE# WE# Data RY/BY VCS Note program address program data WP#/ACC November 23, 2005 S29PL-N_M0_A4 ...
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Addresses CE# OE# WE# Data RY/BY# t VCS V CC Note sector address (for Sector Erase Valid Address for reading status data (see Addresses t AS CE# OE# WE# t WPH Data WE# Controlled Write Cycle ...
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Addresses CE OE# WE# DQ7 DQ6–DQ0 t BUSY RY/BY# Note Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle Figure 13.13 Data# Polling Timings (During Embedded ...
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Enter Erase Embedded Suspend Erasing Erase Erase Suspend WE# DQ6 DQ2 Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6. 13.8.5 Erase and Programming ...
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BGA Ball Capacitance Parameter Symbol OUT C IN2 Notes: 1. Sampled, not 100% tested. 2. Test conditions T A November 23, 2005 S29PL-N_M0_A4 Parameter Description ...
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Commonly Used Terms Term ACC A max A min Asynchronous Autoselect Bank Boot sector Boundary Burst Read Byte CFI Clear Configuration Register Continuous Read Erase Erase Suspend/Erase Resume BGA Linear Read MCP Memory Array MirrorBit™ Technology Page 68 P ...
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Term Page Read Password Protection Persistent Protection Program Program Suspend/Program Resume Read Registers Secured Silicon Sector Protection Sector Simultaneous Operation Synchronous Operation VersatileIO™ Unlock Bypass Word November 23, 2005 S29PL-N_M0_A4 ...
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Term Wraparound Write Write Buffer Write Buffer Programming Write Operation Status Definition Special burst read mode where the read address wraps or returns back to the lowest address ...
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Appendix This section contains information relating to software control or interfacing with the Flash device. For additional information and assistance regarding software, see plore the Web at Command Sequence (Notes) Read (7) Reset (8) Manufacturer ID Auto- Device ID ...
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Command sequence resets device for next command after write- to-buffer operation. 18. Entry commands are needed to enter a specific mode to enable instructions only available within that mode. 19. The Exit command must be issued to reset the ...
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Notes: 1. See (Table 9.1) for description of bus operations. 2. All values are in hexadecimal. 3. Except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the Autoselect commands, and password verify ...
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For further information, please see the CFI Specification (see JEDEC publications JEP137-A and JESD68.01and CFI Publication 100). Please contact your sales office for copies of these documents. Addresses 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Addresses ...
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Addresses 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh November 23, 2005 S29PL-N_M0_A4 ...
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Revisions Revision A0 (February 28, 2005) Initial Release Revision A1 (August 8, 2005) Performance Characteristics Updated Package Options MCP Look-Ahead Connection Diagram Corrected Pinout Memory Map Added Sector and Memory Address Map for S29PL127N Device Operation Table Added Dual ...
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Revision A3 (November 14, 2005) Ordering Information Updated table Valid Combinations Table Updated table Revision A4 (November 23, 2005) Logic Symbols Removed V from the illustrations IO Block Diagram Removed V from the illustration IO PL129N Sector and Memory Address ...
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Type 2 16Mbit (1M Word x 16-bit) 32Mbit (2M Word x 16-bit) 64Mbit (4M Word x 16-bit) 128Mbit (8M Word x 16-bit) Features T Process Technology: CMOS T Organization: x16 bit T Power Supply Voltage: 2.7~3.1V Product Information Density ...
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Pin Description A0 – A19 (16M) A0 – A20 (32M) A0 – A21 (64M) A0 – A22 (128M) 18 Power Up Sequence 1. Apply power. 2. Maintain stable power (V CS1#=high or CS2=low. 19 Timing Diagrams 19.1 Power Up ...
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Functional Description Mode Deselected Deselected Deselected Output Disabled Outputs Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Legend Don’t care (must be low or high state). 21 Absolute ...
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DC and Operating Characteristics 24.1 Common Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage 24.2 16M pSRAM Average Operating Current Standby Current (CMOS) Note: Standby mode is supposed to ...
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Average Operating Current Note: Standby mode is supposed to be set up after at least one active operation after power up. I from the time when standby mode is set up Operating ...
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AC Characteristics (Ta = -40°C to 85°C, V Symbol t Read Cycle Time RC t Address Access Time AA t Chip Select to Output CO t Output Enable to Valid Output OE t UB#, LB# Access Time BA t ...
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Address LB# OE# Data out Note: WE#= Address A1~ OE# DQ15~DQ0 Note: 16Mb A19, 32Mb A20, 64Mb A21, 128Mb ...
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Write Timings Address LB# WE# Data in Data out Address UB#, LB# WE# Data in Data out February 3, 2005 pSRAM_15_A2 ...
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Address LB# WE# Data in Data out Figure 27.6. Timing Waveform of Write Cycle(3) (CS2 Controlled) Address LB# WE# Data in Data out Notes write occurs ...
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Revision Summary 28.1 Revision A0 (February 16, 2004) Initial release 28.2 Revision A1 (June 11, 2004) DC and Operation Characterist ics Updated tables for all densities. 28.3 Revision A2 (February 3, 2005) Product Information Updated table DC Recommended ...
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... Copyright ©2005 Spansion LLC. All rights reserved. Spansion, the Spansion logo, and MirrorBit are trademarks of Spansion LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies S71PL512ND0 MirrorBit™ Flash Family S71PL512ND0_00_A2 December 6, 2005 ...