mh1020 Music Semiconductors, Inc., mh1020 Datasheet
mh1020
Related parts for mh1020
mh1020 Summary of contents
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... MUSIC Semiconductors, the MUSIC logo, and the phrase "MUSIC Semiconductors" are Registered trademarks of MUSIC Semiconductors. MUSIC is a trademark of MUSIC Semiconductors. HARRP HLA packaged Asynchronous Data Recognition and Recall Processor MH1020 DISTINCTIVE CHARACTERISTICS • words • 64-bit per word memory organization • ...
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... GENERAL DESCRIPTION The MH1020 is a 2048x64-bit Content Addressable Memory (CAM), with a 16-bit wide interface. CAMs, also known as associative memories, operate in the converse way to random access memories (RAM). In RAM, the input to the device is an address and the output is the data stored at that address. In CAM, the input is a data sample and the output is a flag to indicate a match and the address of the matching data ...
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... W GND GND DQ8 DQ9 DQ10 DQ11 GND Figure 2: MH1020 High Density Leadless Array (HLA) pinout /E (Chip Enable, Input, TTL) The /E input enables the device while LOW. The falling edge registers the control signals /W, /CM, and /EC. The rising edge locks the daisy chain, turns off the DQ pins, and clocks the Destination and Source Segment counters ...
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Enable, Input, TTL) The /W input selects the direction of data flow during a device cycle. /W LOW selects a Write cycle and /W HIGH selects a Read cycle. /CM (Data/Command Select, Input, TTL) The /CM input selects ...
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FUNCTIONAL DESCRIPTION The Content Addressable Memory (CAM) with 16-bit I/O for network address filtering and translation, virtual memory, data compression, caching, and table lookup applications. The memory consists of static CAM, organized in 64-bit data fields. Each ...
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Mask Registers There are two active Mask registers at any one time, which can be selected to mask comparisons or data writes. Mask Register 1 has both a foreground and background mode to support rapid context switching. Mask Register 2 ...
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DQ15– /CM /EC Rev DQ15–0 /MI /E /FI /W HARRP /FF /CM /EC /MF DQ15–0 /MI /E /FI /W HARRP /FF /CM /EC /MF DQ15–0 /MI /E /FI /W HARRP /FF /CM /EC /MF Figure 3: ...
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OPERATIONAL CHARACTERISTICS Note: Throughout the following, “aaaH” represents a three-digit hexadecimal number “aaa,” while “bbB” represents a two-digit binary number “bb.” All memory locations are written to or read from in 16-bit segments. Segment 0 corresponds to the lowest order ...
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Flag disabled, /MF=/MI and operations directed to Highest-Priority Match locations are ignored. Normal operation of the device is with the /MF enabled. The Match Flag Enable field has no effect on the /MA or /MM output pins or Status Register ...
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Cycle Type /E /CM /W I/O Status Cmd Write Cmd Read OUT OUT OUT OUT OUT OUT OUT OUT OUT HIGH-Z Data Write ...
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CAM Status Validity bits at all memory locations Match and Full Flag outputs IEEE 802.3–802.5 Input Translation CAM/RAM Partitioning Comparison Masking Address register auto-increment or auto-decrement Source and Destination Segment counters count ranges Address register and Next Free Address register ...
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Case Internal Internal /EC(int) /MA(int Case Internal Internal /EC(int) /MA(int ...
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Comparand Register (CR) The 64-bit Comparand register is the default destination for data writes and reads, using the Segment Control register to select which 16-bit segment of the Comparand register loaded or read out. The persistent source ...
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The Memory Array Memory Organization The Memory array is organized into 64-bit words with each word having an additional two validity bits. By default, all words are configured CAM cells. However, bits 8–6 of the Control register ...
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DQ15–0 /EC /MF /MA, /MM I/O Cycles The MH supports four basic I/O cycles: Data Read, Data Write, Command Read, and Command Write. The states of the /W and /CM control inputs determine the type of cycle. ...
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Compare Operations During a Compare operation, the data in the Comparand register is compared to all locations in the Memory array simultaneously. Any Mask register used during compares must be selected beforehand in the Control register. There are two ways ...
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Device Select registers are set to FFFFH), all devices respond to that command write or data write. From then on the daisy chain remains locked in each subsequent cycle as long as /EC is held LOW ...
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TCO PA instruction, and loads its PA register. A Set Full Flag (SFF) instruction advances to the next device in the string and is active ...
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INSTRUCTION SET DESCRIPTIONS Notes: Instruction cycle lengths given in Table 6 on page 23. If f=1, the instruction requires an absolute address to be supplied on the following cycle as a Command write. The value supplied on the second cycle ...
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Instruction: Validity Bit Control (VBC) Binary Op-Code: 0000 f100 00dd dvvv f Address Field flag ddd Destination of data vvv Validity setting for Memory location The VBC instruction sets the Validity bits at the selected memory locations to the selected ...
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INSTRUCTION SET SUMMARY Mnemonic Format: INS dst, src[msk], val INS: Instruction mnemonic dst: Destination of the data src: Source of the data msk: Mask register used val: Validity condition set at the location written Instruction: Select Persistent Source Operation Mnemonic ...
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Instruction: Data Move (continued) Operation Mnemonic Mask Register 2 from: Comparand Register MOV MR2,CR Mask Register 1 MOV MR2,MR1 No Operation NOP Memory at Address Reg. MOV MR2,[AR] Memory at Address MOV MR2,aaaH Mem. at Highest-Prio. Match MOV MR2,HM Memory ...
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Instruction Cycle Lengths Cycle Length Command Write TCO reg (except CT) TCO CT (non-reset, HMA invalid) Short SPS, SPD, SFR SBR, RSC MOV reg, reg MOV reg, mem TCO CT (reset) Medium VBC (NFA invalid) SFT NOP MOV mem, reg ...
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REGISTER BIT ASSIGNMENTS Control Register Bits Bit(s) Name Description 15 RST 0 = Reset 14:13 Match Flag 00 = Enable 01 = Disable 10 = Reserved Change 12:11 Full Flag 00 = Enable 01 = Disable 10 ...
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Next Free Address Bits Bit(s) Name Description 15:11 PA4–0 Page Address 10:0 NF10-0 Next Free Address Note: The Next Free Address register is read only, and is accessed by performing a Command Read cycle immediately following a TCO NF instruction. ...
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ELECTRICAL Supply Voltage -0.5 to 4.6 Volts Voltage on all other pins -0.5 to VCC +0.5 Volts (-2 Volts for 10 ns, measured at the 50% point) Temperature under bias -55° 125° C Storage Temperature -55° ...
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AC Test Conditions Input Signal Transitions 0.0 Volts to 3.0 Volts Input Signal Rise Time < Input Signal Fall Time < Input Timing Reference Level 1.5 Volts Output Timing Reference Level 1.5 Volts Table 7: AC ...
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Switching Characteristics No. Symbol Parameter 1 t ELEL Chip Enable Compare Cycle Time t ELEH 2 Chip Enable LOW Pulse Width 3 t EHEL Chip Enable HIGH Pulse Width 4 t CVEL Control Input to Chip Enable LOW Setup Time ...
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TIMING DIAGRAMS Figure 12: Read Cycle /E /W /CM /EC /MI /MF /MA, /MM Rev. 1 ...
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PACKAGE TOP VIEW D Pin 1 indicator SIDE VIEW Symbol Min A 0. 0.15 e1 0.50 BSC e2 1.00 BSC Notes: 1. All dimensions are in millimeters. 2. ’e1’ and ’e2’ and ’e3’ represent the basic land ...
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... ORDERING INFORMATION Organization Part Number MH1020 2048 x 64 http: //www.musicsemi.com Rev. 1 Cycle Time Package 70 ns HLA email: info@musicsemi.com 31 Temperature 0–70° C ...