l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet

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l-fw32206t100

Manufacturer Part Number
l-fw32206t100
Description
1394a Phy/link Open Host Controller
Manufacturer
ETC-unknow
Datasheet
Features
FW322 06 T100
1394a PCI PHY/Link Open Host Controller
1394a-2000 OHCI link and PHY core function in a sin-
gle device:
— 100-pin TQFP package (also available in a lead-free
— Single-chip link and PHY enable smaller, simpler,
— Enables lower system costs
— Leverages proven 1394a-2000 PHY core design
— Demonstrated compatibility with current Microsoft
— Demonstrated interoperability with existing, as well
— Feature-rich implementation for high performance in
— Supports low-power system designs (CMOS imple-
OHCI:
— Complies with the 1394 OHCI 1.1 Specification
— OHCI 1.0 backwards compatible—configurable via
— Complies with Microsoft Windows logo program
— Listed on Windows hardware compatibility list
— Compatible with Microsoft Windows and MacOS
— 4 Kbyte isochronous transmit FIFO
— 2 Kbyte asynchronous transmit FIFO
— 4 Kbyte isochronous receive FIFO
— 2 Kbyte asynchronous receive FIFO
— Dedicated asynchronous and isochronous
— Eight isochronous transmit contexts
— Eight isochronous receive contexts
— Prefetches isochronous transmit data
— Supports posted write transactions
— Supports parallel processing of incoming physical
— Supports notification (via interrupt) of a failed
— Information normally in the EEPROM can be pro-
1394a-2000 PHY core:
— Compliant with IEEE
grammed into the system BIOS.
package; see ordering information on page 85.)
more efficient motherboard and add-in card designs
Windows
as older, 1394 consumer electronics and peripherals
products
common applications
mentation, power management features)
EEPROM to operate in either OHCI 1.0 or OHCI 1.1
mode
system and device requirements
http://www.microsoft.com/hcl/results.asp
operating systems
descriptor-based DMA engines
read and write requests
register access
High Performance Serial Bus (Supplement)
®
drivers and common applications
®
1394a-2000, Standard for a
®
Note: This device does not support D3cold wakeup,
— Provides two fully compliant cable ports, each
— Supports extended BIAS_HANDSHAKE time for
— While unpowered and connected to the bus, will not
— Does not require external filter capacitor for PLL
— Supports link-on as a part of the internal
— 25 MHz crystal oscillator and internal PLL provide a
— Interoperable across 1394 cable with 1394 physical
— Provides node power-class information signaling for
— Supports ack-accelerated arbitration and fly-by
— Supports arbitrated short bus reset to improve
— Fully supports suspend/resume
— Supports connection debounce
— Supports multispeed packet concatenation
— Supports PHY pinging and remote PHY access
— Reports cable power fail interrupt when voltage at
Link:
— Cycle master and isochronous resource manager
— Supports 1394a-2000 acceleration features
PCI:
— Revision 2.2 compliant
— 33 MHz/32-bit operation
— Programmable burst size thresholds for PCI data
— Supports optimized memory read line, memory read
— Supports PCI Bus Power Management Interface
supporting 400 Mbits/s, 200 Mbits/s, and
100 Mbits/s traffic
enhanced interoperability with camcorders
drive TPBIAS on a connected port even if receiving
incoming bias voltage on that port
PHY core-link interface
50 MHz internal link-layer controller clock as well
as transmit/receive data at 100 Mbits/s, 200 Mbits/s,
and 400 Mbits/s.
layers (PHY core) using 5 V supplies
system power management
concatenation
utilization of the bus
packets
CPS pin falls below 7.5 V
capable
transfer
multiple, and memory write invalidate burst
commands
Specification v.1.1.
CLKRUN protocol, mini PCI
CardBus applications. Use the FW322 06 120-pin
TQFP device if one or more of these features are
needed.
Data Sheet, Rev. 1
®
applications, and
December 2005

Related parts for l-fw32206t100

l-fw32206t100 Summary of contents

Page 1

... Does not require external filter capacitor for PLL — Supports link- part of the internal PHY core-link interface — 25 MHz crystal oscillator and internal PLL provide a 50 MHz internal link-layer controller clock as well as transmit/receive data at 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s. ...

Page 2

... Vendor ID Register ...........................................................................................................................................22 Device ID Register ............................................................................................................................................22 PCI Command Register ....................................................................................................................................23 PCI Status Register ..........................................................................................................................................24 Class Code and Revision ID Registers.............................................................................................................25 Latency Timer and Cache Line Size Register ..................................................................................................25 Header Type and BIST Register.......................................................................................................................26 OHCI Base Address Register ...........................................................................................................................26 PCI Subsystem Identification Register .............................................................................................................27 PCI Power Management Capabilities Pointer Register ....................................................................................27 Interrupt Line and Pin Register ...

Page 3

... Asynchronous Context Command Pointer Register .........................................................................................62 Isochronous Transmit Context Control (IT DMA ContextControl) Register ......................................................63 Isochronous Transmit Context Command Pointer Register..............................................................................64 Isochronous Receive Context Control (IR DMA ContextControl) Register .......................................................65 Isochronous Receive Context Command Pointer Register...............................................................................66 Isochronous Receive Context Match (IR DMA ContextMatch) Register...........................................................67 FW322 Vendor-Specific Registers....................................................................................................................68 Isochronous DMA Control ...

Page 4

... Table 4. PCI Command Register Description ........................................................................................................ 23 Table 5. PCI Status Register ................................................................................................................................. 24 Table 6. Class Code and Revision ID Register Description .................................................................................. 25 Table 7. Latency Timer and Class Cache Line Size Register Description ........................................................... 25 Table 8. Header Type and BIST Register Description .......................................................................................... 26 Table 9. OHCI Base Address Register Description ............................................................................................... 26 Table 10. PCI Subsystem Identification Register Description ............................................................................... 27 Table 11 ...

Page 5

... Table 65. PHY Core Register Fields ..................................................................................................................... 72 Table 66. PHY Core Register Page 0: Port Status Page ...................................................................................... 74 Table 67. PHY Core Register Port Status Page Fields ........................................................................................ 75 Table 68. PHY Core Register Page 1: Vendor Identification Page ....................................................................... 76 Table 69. PHY Core Register Vendor Identification Page Fields .......................................................................... 76 Table 70. ac Characteristics of Serial EEPROM Interface Signals ....................................................................... 78 Table 71 ...

Page 6

... V operation tolerant inputs FW322 Functional Overview The FW322 is a high-performance, PCI bus-based open host controller designed by Agere Systems Inc. for imple- mentation of IEEE 1394a-2000 compliant systems and devices. Link-layer functions are handled by the FW322, uti- lizing the on-chip 1394a-2000 compliant link core and physical layer core. A high-performance and cost-effective solution for connecting and servicing multiple IEEE 1394 (both 1394-1995 and 1394a-2000) peripheral devices can be realized using this PHY/link OHCI device ...

Page 7

... PCI BUS PCI Core The PCI core (shown in Figure 2) serves as the interface to the PCI bus. It contains the state machines that allow the FW322 to respond properly when it is the target of the transaction. Also, during 1394 packet transmission or reception, the PCI core arbitrates for the PCI bus and enables the FW322 to become the bus master for reading the different buffer descriptors and management of the actual data transfers to/from host system memory ...

Page 8

... The PCI interface provides an interface between the OHCI blocks and the PCI core. It contains an arbiter to select the appropriate OHCI data engine to gain access to the PCI core. In addition, the PCI interface includes a register select function to decode slave accesses to the OHCI core and select data from appropriate sources ...

Page 9

... Fetch a descriptor block from host memory. 2. Fetch data specified by the descriptor block from host memory, and place it into the isochronous transmit FIFO. 3. Data in FIFO is read by the link and sent to the PHY core device interface. Isochronous Receive DMA (IRDMA) The isochronous receive DMA (IRDMA) module moves data from the isochronous receive FIFO to host memory ...

Page 10

... Fetch complete buffer descriptor block from host memory. 2. Get data from system memory and store into asynchronous transmit (AT) FIFO. 3. Request transfer of data from FIFO to the link core. 4. Handle retries, if any. 5. Handle errors in steps End the transfer if there are no errors. ...

Page 11

... Isochronous Control Timer: contains the logic for the 1394 cycle timer. DataMUX: pipes 1394 data to and from various modules. Interface Control: contains interrupt and registers for the link core. Interfaces with the slave control block of the PCI core. PHY-Link Interface: interfaces with the 1394 physical layer. ...

Page 12

... Based on data received from the OHCI block, the link will form packet headers for the 1394 bus. The link will alert the PHY core regarding the availability of the outbound data the link’s function to generate CRC for the outbound data ...

Page 13

... The 49.152 MHz clock signal is also supplied to the associated link layer controller (LLC) for synchroniza- tion of the link with the PHY core and is used for resynchronization of the received data. The PHY/link interface is a direct connection and does not provide isolation ...

Page 14

... SelfID packet is set to the value of the PC2 pin. The two most significant bits (21 and 22) in the Pwr field are set to a default of 00. The PC2 pin is tied low or high to create a Pwr field of 000 (PC2 low) or 001 (PC2 high). See Section 4.3.4.1 of the IEEE 1394a-2000 specification for additional details ...

Page 15

... SS PCI_CBEN[3] 23 PCI_IDSEL 24 PCI_AD[23] 25 Note: Active-low signals within this document are indicated following the symbol names. Figure 6. Pin Assignments for the FW322 06 T100 Agere Systems Inc. 1394a PCI PHY/Link Open Host Controller PIN #1 IDENTIFIER AGERE FW322 06 T100 FW322 06 T100 V 75 ...

Page 16

... PCI_AD[17] 35 PCI_AD[16] 36 PCI_CBEN[2] 37 PCI_FRAMEN * Active-low signals within this document are indicated following the symbol names Type I Test. Used by Agere for device manufacturing testing. This pin must be tied high for normal operation. Do not tie this pin Test. Used by Agere for device manufacturing testing. Tie to V normal operation ...

Page 17

... PCI Signaling Indicator. For PCI applications that use a universal expansion board (see PCI Local Bus Specification, Rev. 2.2, Sec- tion 4.1.1), connect this pin to the VI/O pin. For other cases, con- nect this pin to 3.3 V for PCI buses using 3.3 V signaling for PCI buses using 5 V signaling. FW322 06 T100 ...

Page 18

... TPB1– 78 TPB1+ 79 TPA1– 80 TPA1+ * Active-low signals within this document are indicated following the symbol names Type I Power-Class Indicator. On hardware reset (RESETN), this input sets the default value of the least significant bit in the Power Class field (Pwr) in the SelfID packet (see Section 4.3.4.1 of the 1394 a- 2000 Specification) ...

Page 19

... PLLV DD 92 PLLV SS * Active-low signals within this document are indicated following the symbol names. Agere Systems Inc. 1394a PCI PHY/Link Open Host Controller Type Analog I/O Port 1, Twisted-Pair Bias. TPBIAS1 provides the 1.86 V nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers and for sending a valid cable connection signal to the remote nodes. When the FW322’ ...

Page 20

... Active-low signals within this document are indicated following the symbol names. Note: For those applications when one or more FW322 ports are not wired to a connector, those unused ports may be left unconnected without normal termination. When a port does not have a cable connected, internal connect-detect circuitry will keep the port in a disconnected state. ...

Page 21

... Minimum Grant [18h] [0Ch minor revision number of the FW322 06 T100 and may be any value from 0 hex to F hex. † Values for this register can be loaded from a serial EEPROM during the powerup sequence. Agere Systems Inc. 1394a PCI PHY/Link Open Host Controller ...

Page 22

... Offset: 00h Default: 11C1h Type: Read only Reference: PCI Local Bus Specification, Rev. 2.2, Section 6.2.1 Device ID Register The Device ID register contains a value assigned to the FW322 by Agere. The device identification for the FW322 is 5811h. Offset: 02h Default: 5811h Type: Read only Reference: PCI Local Bus Specification, Rev. 2.2, Section 6.2.1 ...

Page 23

... Data Sheet, Rev. 1 December 2005 Internal Registers (continued) PCI Command Register The Command register provides control over the FW322 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification the following bit descriptions. Offset: 04h Default: ...

Page 24

... FW322 06 T100 1394a PCI PHY/Link Open Host Controller Internal Registers (continued) PCI Status Register The Status register provides status information for PCI bus related events. All bit functions adhere to the definitions in the PCI Local Bus Specification, v.2.2, Table 6.2. Offset: 06h Default: 0290h ...

Page 25

... PGMIF 7:0 CHIPREV * minor revision number of the FW322 06 T100 and may be any value from 0 hex to F hex. Latency Timer and Cache Line Size Register The Latency Timer and Class Cache Line Size register is programmed by host BIOS to indicate system cache line size and the latency timer associated with the FW322 serial EEPROM is detected, then the contents of this register are loaded from the serial EEPROM interface after a PCI reset ...

Page 26

... The OHCI Base Address register is programmed with a base address referencing the memory-mapped OHCI con- trol. When BIOS writes all 1s to this register, the value read back is FFFF F000h, indicating that 4 Kbytes of mem- ory address space are required for the OHCI registers. ...

Page 27

... EEPROM is not interfaced to the FW322 06, bit 0 (SubSystemWriteEn) of the PCI Config register, offset 4Ch can be set to enable writes to the PCI Subsystem ID and PCI Subsystem Vendor ID so that these registers can be customized to the correct ID values. After the IDs have been written, the SubSystemWriteEn bit should be reset to protect the data from being overwritten ...

Page 28

... The MIN_GNT and MAX_LAT register is used to communicate to the system the desired setting of the Latency Timer register serial EEPROM is detected, then the contents of this register are loaded from the serial EEPROM interface after a PCI reset serial EEPROM is detected, then this register returns a default value that corresponds to the MIN_GNT = 0Ch, MAX_LAT = 18h. ...

Page 29

... Table 13. PCI OHCI Control Register Description Bit Field Name 31:1 Reserved 0 GLOBAL_SWAP Capability ID and Next Item Pointer Register The Capability ID and Next Item Pointer register identifies the linked list capability item and provides a pointer to the next capability item. Offset: 44h Default: 0001h Type: Read only Reference: PCI Local Bus Specification, Rev ...

Page 30

... Power Management Capabilities Register The Power Management Capabilities register indicates the capabilities of the FW322 related to PCI power man- agement. The default value of this register can be selectively programmed by the serial EEPROM. However, the D3cold and AUX_PWR fields cannot be changed from the default the EEPROM. ...

Page 31

... The Power Management Control and Status register implements the control and status of the PCI power manage- ment function. This register is not affected by the internally generated reset caused by the transition from the D3hot to D0 state. All bits within this register, will be reset by a PCI reset. ...

Page 32

... Software uses the DATA_SELECT and DATA_SCALE fields within the Power Management Control and Status register to select and scale the desired PM data entry. Note that if the serial EEPROM is used to program nonzero values into PM DATA, then the AUX_PWR field should be programmed to a zero value via the serial EEPROM and vice versa ...

Page 33

... RegisterSet causes the corresponding bit in the register to be set, while a 0 bit leaves the corresponding bit unaffected bit written to RegisterClear causes the corresponding bit in the register to be reset, while a 0 bit leaves the corresponding bit unaffected. Typically, a read from either RegisterSet or RegisterClear returns the con- tents of the set or clear register ...

Page 34

... FW322 06 T100 1394a PCI PHY/Link Open Host Controller Internal Registers (continued) Table 18. OHCI Register Map (continued) DMA Register Name Context SelfID SelfID Buffer SelfID Count Reserved — Isochronous Receive Channel Mask High Isochronous Receive Channel Mask Low Interrupt Event Interrupt Mask ...

Page 35

... Context Control Context 0:7 Reserved Command Pointer Isochronous Context Control Receive Context n Reserved n = 0:7 Command Pointer Context Match Reserved Agere Systems Inc. 1394a PCI PHY/Link Open Host Controller Abbreviation Offset ContextControlSet 180h ContextControlClear 184h — 188h CommandPtr 18Ch — 190h:19Ch ContextControlSet 1A0h ...

Page 36

... OHCI Version Register This register indicates the OHCI version supported, and whether or not the serial EEPROM is present. To support backwards compatibility with existing hardware and software, the version and revision fields default to 8’h01 and 8’h00 respectively. These values denote compatibility with version 1.0 of the OHCI specification. However, both the version and revision fields are programmable via the serial EEPROM. This functionality allows these fields to be optionally updated to 8’ ...

Page 37

... Data Sheet, Rev. 1 December 2005 Internal Registers (continued) GUID ROM Register The GUID ROM register is used to access the serial EEPROM, and is only applicable if bit 24 (GUID_ROM) in the OHCI Version register is set. Offset: 04h Default: 00XX 0000h Reference: 1394 Open Host Controller Interface Specification, Rev. 1.1, Section 5.3 Table 20 ...

Page 38

... CSR Compare Register The CSR Compare register is used to access the bus management CSR registers from the host through compare- swap operations. This register contains the data to be compared with the existing value of the CSR resource. Offset: 10h Default: XXXX XXXXh Reference: 1394 Open Host Controller Interface Specification, Rev ...

Page 39

... Data Sheet, Rev. 1 December 2005 Internal Registers (continued) Configuration ROM Header Register The Configuration ROM Header register externally maps to the first quadlet of the 1394 configuration ROM, offset 48’hFFFF_F000_0400. Offset: 18h Default: 0000 0000h Reference: 1394 Open Host Controller Interface Specification, Rev. 1.1, Section 5.5.2 Table 25 ...

Page 40

... Open Host Controller Interface Specification, Rev. 1.1, Section 5.5.3 Table 26. Bus Identification Register Description Bit Field Name 31—0 busID Bus Options Register The Bus Options register externally maps to the second quadlet of the Bus_Info_Block and is 1394 addressable at FFFF_F000_0408. Offset: 20h Default: 0000 A002h Reference: 1394 Open Host Controller Interface Specification, Rev ...

Page 41

... EEPROM is detected, then the contents of this register are loaded through the serial EEPROM interface after a PCI reset serial EEPROM is detected, then the contents of this register can be loaded with a single PCI write to either of two configuration registers, executed after a PCI reset. The two configuration registers are located at offset 0x70, for new PCI applications, and offset 0x80, for backward compatibility with FW322 05 PCI applications only ...

Page 42

... The Configuration ROM Mapping register contains the start address within system memory that maps to the start address of 1394 configuration ROM for this node. Offset: 34h Default: 0000 0000h Reference: 1394 Open Host Controller Interface Specification, Rev. 1.1, Section 5.5.6 Table 30. Configuration ROM Mapping Register Description Bit Field Name 31:10 configROMaddr 9:0 ...

Page 43

... Data Sheet, Rev. 1 December 2005 Internal Registers (continued) Posted Write Address Low Register The Posted Write Address Low register is used to communicate error information if a write request is posted and an error occurs while writing the posted data packet. Offset: 38h Default: XXXX XXXXh Reference: 1394 Open Host Controller Interface Specification, Rev ...

Page 44

... FW322 06 T100 1394a PCI PHY/Link Open Host Controller Internal Registers (continued) Host Controller Control Register The Host Controller Control set/clear register pair provides flags for controlling the OHCI portion of the FW322. Offset: 50h set register 54h clear register Default: X08X 0000h Reference: 1394 Open Host Controller Interface Specification, Rev ...

Page 45

... PCI PHY/Link Open Host Controller Type RSU This bit is cleared either a hardware or software reset. Soft- ware must set this bit to 1 when the system is ready to begin oper- ation and then force a bus reset. This bit is necessary to keep other nodes from sending transactions before the local system is ready ...

Page 46

... PCI PHY/Link Open Host Controller Internal Registers (continued) SelfID Buffer Pointer Register The SelfID Buffer Pointer register points to the 2 Kbyte aligned base address of the buffer in host memory where the SelfID packets are stored during bus initialization. Bits 31:11 are read/write accessible. Offset: 64h ...

Page 47

... Isochronous Receive Multiple Channel Mask High (IRMultiChanMaskHi) Register The Isochronous Receive Multiple Channel Mask High set/clear register is used to enable packet receives from the upper 32 isochronous data channels. A read from either the set register or clear register returns the content of the Isochronous Receive Multiple Channel Mask High register. ...

Page 48

... The only mechanism to clear the bits in this register is to write the corresponding bit in the clear register. Reading the IntEventSet register returns the current state of the IntEvent register. Reading the IntEventClear register returns the masked version of the IntEvent register, i ...

Page 49

... Indicates the PHY core requests an interrupt through a status transfer. RSCU Indicates that an OHCI register access failed due to a missing SCLK clock signal from the PHY. When a register access fails, this bit will be set before the next register access. RSCU Indicates that the PHY core chip has entered bus reset mode. ...

Page 50

... The Interrupt Mask set/clear register is used to enable/disable the various FW322 interrupt sources. Reads from either the set register or the clear register always return the contents of the Interrupt Mask register. In all cases except masterIntEnable (bit 31), the enables for each interrupt event align with the Interrupt Event (IntEvent) register bits (see Table 39) ...

Page 51

... Table 40. Interrupt Mask Register Description (continued) Bit Field Name 9 lockRespErr 8 postedWriteErr 7 isochRx 6 isochTx 5 RSPkt 4 RQPkt 3 ARRS 2 ARRQ 1 respTxComplete 0 reqTxComplete Agere Systems Inc. 1394a PCI PHY/Link Open Host Controller Type RSCU When set, these bits enable the corresponding IntEvent register bits to generate a processor interrupt. FW322 06 T100 Description 51 ...

Page 52

... The interrupt bits are set by an asserting edge of the corresponding interrupt signal writing the corresponding bit in the set register. The only mechanism to clear the bits in this register is to write the corresponding bit in the clear register. ...

Page 53

... The Isochronous Transmit Interrupt Mask set/clear register is used to enable the isochTx interrupt source on a per-channel basis. Reads from either the set register or the clear register, always return the contents of the Isochronous Transmit Interrupt Mask register. In all cases, the enables for each interrupt event align with the event register bits detailed in Table 42 ...

Page 54

... The interrupt bits are set by an asserting edge of the corresponding interrupt signal writing the corresponding bit in the set register. The only mechanism to clear the bits in this register is to write the corresponding bit in the clear reg- ister. ...

Page 55

... The Isochronous Receive Interrupt Mask set/clear register is used to enable the isochRx interrupt source on a per-channel basis. Reads from either the set register or the clear register always return the contents of the Isochronous Transmit Interrupt Mask register. In all cases, the enables for each interrupt event correspond to the isoRecvIntEvent register bits ...

Page 56

... FW322 06 T100 1394a PCI PHY/Link Open Host Controller Internal Registers (continued) Link Control Register The Link Control register provides flags to enable and configure the link core cycle timer and receiver portions of the FW322. Offset: E0h set register E4h clear register Default: ...

Page 57

... Node Identification Register The Node Identification register contains the address of the node on which the OHCI resides, and indicates the valid node number status. The 16-bit combination of the busNumber field (bits 15:6) and the NodeNumber field (bits 5:0) is referred to as the node ID. Offset: ...

Page 58

... When the FW322 is not cycle master, this register is loaded with the data field in an incoming cycle start. In the event that the cycle start message is not received, the fields can continue incrementing on their own (if programmed) to maintain a local time reference. ...

Page 59

... Table 50. Asynchronous Request Filter Low Register Description Bit Field Name Type 31:0 asynReqResourceN RSCU If this bit is set for local bus node number N (where N = the bit number from Agere Systems Inc. 1394a PCI PHY/Link Open Host Controller Description nonlocal bus nodes are accepted and the values of all asynReqResourceN bits will be ignored ...

Page 60

... IDs. When a packet is destined for the physical request context and the node ID has been compared against the ARRQ registers, then the comparison is done again with this register. If the bit corresponding to the node ID is not set in this register, then the request is handled by the ARRQ context instead of the physical request context. ...

Page 61

... Data Sheet, Rev. 1 December 2005 Internal Registers (continued) Asynchronous Context Control Register The Asynchronous Context Control set/clear register controls the state and indicates status of the DMA context. Offset: 180h set register (ATRQ) 184h clear register (ATRQ) 1A0h set register (ATRS) 1A4h ...

Page 62

... PCI PHY/Link Open Host Controller Internal Registers (continued) Asynchronous Context Command Pointer Register The Asynchronous Context Command Pointer register contains a pointer to the address of the first descriptor block that the FW322 accesses when software enables the context by setting the Asynchronous Context Control register bit 15 (run). Offset: ...

Page 63

... Isochronous Transmit Context Control (IT DMA ContextControl) Register The Isochronous Transmit Context Control set/clear register controls options, state, and status for the isochronous transmit DMA contexts. The n value in the following register addresses indicates the context number (n = 0:7). Offset: 200h + ( set register ...

Page 64

... The Isochronous Transmit Context Command Pointer register contains a pointer to the address of the first descrip- tor block that the FW322 accesses when software enables an isochronous transmit context by setting the Isochro- nous Transmit Context Control register bit 15 (run). The n value in the following register addresses indicates the context number (n = 0:7). ...

Page 65

... Channel Mask registers. If more than one Isochronous Receive Context Control register has this bit set, then results are undefined. The value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set to 1. RSC When this bit is set, received packets are separated into first and second payload and streamed independently to the first buffer series and second buffer series (see OHCI v ...

Page 66

... Isochronous Receive Context Command Pointer Register The Isochronous Receive Context Command Pointer register contains a pointer to the address of the first descriptor block that the FW322 accesses when software enables an isochronous receive context by setting the Isochronous Receive Context Control register bit 15 (run). The n value in the following register addresses indicates the context number (n = 0:7) ...

Page 67

... December 2005 Internal Registers (continued) Isochronous Receive Context Match (IR DMA ContextMatch) Register The Isochronous Receive Context Match register is used to control on which isochronous cycle the context should start. The register is also used to control which packets are accepted by the context. Offset: 410Ch + ( ...

Page 68

... The fields in this register control when the isochronous DMA engines access the PCI bus and how much data they will attempt to move in a single PCI transaction. The actual PCI burst sizes will also be affected by 1394 packet size, host memory buffer size, FIFO constraints, and the PCI cache line size. ...

Page 69

... The fields in this register control the functionality within the asynchronous and physical DMA engines. Accesses to the PCI bus and how much data the DMA engines will attempt to move in a single PCI transaction can be con- trolled. The actual PCI burst sizes will also be affected by 1394 packet size, host memory buffer size, FIFO con- straints, and the PCI cache line size ...

Page 70

... FW322 06 T100 1394a PCI PHY/Link Open Host Controller Internal Registers (continued) Link Options The values in this register provide low-level control of configurable features within the FW322 that are beyond those stated in 1394 and OHCI specifications. Offset: 840h Default: 0000 0020h Table 63. Link Options Register Description ...

Page 71

... Data Sheet, Rev. 1 December 2005 Internal Register Configuration PHY Core Register Map The PHY Core register map is shown below in Table 64. Reference: IEEE Standard 1394a-2000, Annex J2 Table 64. PHY Core Register Map Address Bit 0 Bit 1 0000 2 0001 RHB IBR 2 0010 Extended (7) 2 0011 ...

Page 72

... Link Active. Cleared or set by software to control the value of the L bit transmitted in the node’s SelfID packet 0, which will be the logical AND of this bit and LPS active. See Cleared or set by software to control the value of the C bit transmit- description ted in the SelfID packet. Powerup reset value is 0. 000 The difference between the fastest and slowest repeater data delay = [(Jitter + 1) * 20] ns ...

Page 73

... Loop Detect. A write of one to this bit clears it to zero. 1 Cable Power Failure Detect. Set to one when the PS bit changes from one to zero. A write of one to this bit clears it to zero. 0 Arbitration State Machine Time-Out. A write of one to this bit clears it to zero (see MAX_ARB_STATE_TIME). ...

Page 74

... Internal Register Configuration The port status page is used to access configuration and status information for each of the PHY core’s ports. The port is selected by writing zero to Page_select and the desired port number to Port_select in the PHY Core register at address 0111 . The format of the port status page is illustrated by Table 66 below; reserved fields are shown as 2 XXXXX ...

Page 75

... Data Sheet, Rev. 1 December 2005 Internal Register Configuration The meaning of the register fields in the port status page are defined by Table 67 below. Table 67. PHY Core Register Port Status Page Fields Field Size Type AStat 2 R BStat 2 R Child 1 R Connected 1 R Bias ...

Page 76

... Compliance_level 8 r Vendor_ID 24 r Product_ID minor revision number of the FW322 06 T100 and may be any value from 0 hex to F hex. Note: The vendor-dependent page provides access to information used in the manufacturing test of the FW322. 76 (continued) Contents Bit 2 Bit 3 Bit 4 Compliance_level Vendor_ID ...

Page 77

... Minimizing the loop area minimizes the effect of the resonant current that flows in this resonant circuit. This layout unit (crystal and load capacitors) should then be placed as close as possible to the PHY XI and XO terminals to minimize trace lengths. Vias should not be used to route the XI and XO signals. Agere Systems Inc. ...

Page 78

... EEPROM. ROM_AD is bidirectional and is used for serial data/control transfers between the FW322 and the external EEPROM. The FW322 uses this interface to read the contents of the serial EEPROM in response to the first PCI reset after powerup. The FW322 also makes the serial ROM interface visible to software through the OHCI defined GUID ROM register ...

Page 79

... ROM_AD IN tDATA_VALID ROM_AD OUT ROM_CLK: serial clock, ROM_AD: serial data I/O. ROM_CLK ROM_AD 8TH BIT WORD n ROM_CLK: serial clock, ROM_AD: serial data I/O. ROM_AD ROM_CLK ROM_CLK: serial clock, ROM_AD: serial data I/O. Agere Systems Inc. 1394a PCI PHY/Link Open Host Controller tPW_LOW tPW_HIGH tPW_LOW ...

Page 80

... FW322 06 T100 1394a PCI PHY/Link Open Host Controller ac Characteristics (continued) ROM_AD ROM_CLK ROM_CLK: serial clock, ROM_AD: serial data I/O. ROM_CLK DATA IN DATA OUT START ROM_CLK: serial clock START Figure 11. Start and Stop Definition 1 Figure 12. Output Acknowledge Data Sheet, Rev. 1 December 2005 STOP 1311 (F) R ...

Page 81

... Up to three reflows may be performed using a temperature profile that meets the requirements of Table 3 in stan- dard IPC/JEDEC J-STD-020. The requirements of IPC/JEDEC J-STD-033 must be met. The maximum allowable body temperature for the FW322 is 220 °C —225 °C. This is the actual tolerance that Agere uses to test the devices during preconditioning. ...

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... Common-mode Voltage Nonsource Power Mode* Receive Input Jitter Receive Input Skew Between TPA and TPB cable inputs, Between TPA and TPB cable inputs, Between TPA and TPB cable inputs, Positive Arbitration Comparator Input Threshold Voltage Negative Arbitration Comparator Input Threshold Voltage ...

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... TPA+, TPA−, TPB+, TPB− Common-mode Speed Signaling Current, TPB+, TPB− * Limits are defined as the algebraic sum of TPA+ and TPA− driver currents. Limits also apply to TPB+ and TPB− as the algebraic sum of driver currents. Table 74. Device Characteristics Parameter ...

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... FW322 06 T100 1394a PCI PHY/Link Open Host Controller Timing Characteristics Table 75. Switching Characteristics Symbol Parameter — Jitter, Transmit — Transmit Skew t Rise Time, Transmit (TPA/TPB Fall Time, Transmit (TPA/TPB) f Table 76. Clock Characteristics Parameter External Clock Source Frequency 84 Measured Test Conditions ...

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... Agere Systems lead-free devices are fully compliant with the Restriction of Hazardous Substances (RoHS) directive that restricts the content of six hazardous substances in electronic equipment in the European Union. Beginning July 1, 2006, electronic equipment sold in the Euro- pean Union must be manufactured in accordance with the standards set by the RoHS directive. ...

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... EUROPE: Tel. (44) 1344 296 400 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere, Agere Systems, and the Agere logo are registered trademarks of Agere Systems Inc. Copyright © 2005 Agere Systems Inc. ...

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