am85c30 Advanced Micro Devices, am85c30 Datasheet
am85c30
Available stocks
Related parts for am85c30
am85c30 Summary of contents
Page 1
... The Am85C30 is easy to use due to a variety of sophisti- cated internal functions, including on-chip baud rate — Programmable CRC generators and checkers — ...
Page 2
... AMD Enhancements that allow the Am85C30 to be used more effectively in high-speed applications include bit SDLC/HDLC frame status FIFO array A 14-bit SDLC/HDLC frame byte counter Automatic SDLC/HDLC opening frame flag transmission TxD pin forced High in SDLC NRZI mode after closing flag ...
Page 3
... RTxCA SYNCA W/REQA A/B DTR/REQA CE RTSA CTSA D/C DCDA TxDB INT RxDB INTACK TRxCB IEI RTxCB IE0 SYNCB W/REQB DTR/REQB RTSB CTSB DCDB +5 V GND PCLK Am85C30 AMD PLCC, LCC A D GND 35 W/REQB 34 SYNCB 33 RTxCB 32 RxDB 31 TRxCB 30 ...
Page 4
... AM85C30 -10 P DEVICE NUMBER/DESCRIPTION Am85C30 Enhanced Serial Communications Controller Valid Combinations AM85C30-8 AM85C30-10 PC, JC AM85C30- OPTIONAL PROCESSING Blank = Standard Processing TEMPERATURE RANGE C = Commercial (0 to +70 C) PACKAGE TYPE P = 40-Pin Plastic DIP (PD 040 44-Pin Plastic Leaded Chip Carrier (PL 044) SPEED OPTION - ...
Page 5
... J = 44-Pin Leadless Chip Carrier (PL 044) SPEED OPTION - MHz -16 = 16.384 MHz Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult JI the local AMD sales office to confirm availability of specific valid combinations and check on newly released combinations. Am85C30 AMD 5 ...
Page 6
... Products List) products are fully compliant with MIL-STD-883 requirements. The order number (Valid Combination) is formed by a combination of: AM85C30 -10 B DEVICE NUMBER/DESCRIPTION Am85C30 Enhanced Serial Communications Controller Valid Combinations AM85C30-8 AM85C30-10 AM85C30- LEAD FINISH A = Hot Solder Dip PACKAGE TYPE U = 44-Pin Leadless Chip Carrier (CL 044 40-Pin Ceramic DIP (CD 040) DEVICE CLASS /B = Class B SPEED OPTION - ...
Page 7
... SYNC characters are recognized. The SYNC condition is not latched, so these outputs are active each time a SYNC pattern is recognized (regardless of character boundaries). In SDLC mode, these pins act as outputs and are valid on receipt of a flag. Am85C30 AMD 7 ...
Page 8
... GND Ground PCLK Clock (Input) This is the master SCC clock used to synchronize inter- nal signals. PCLK is not required to have any phase relationship with the master system clock. PCLK is a TTL- level signal. Maximum transmit rate is 1/4 PCLK. VCC + 5 V Power Supply Am85C30 ...
Page 9
... All other registers are paired (one for each channel). Internal Channel Control A Logic Registers Internal Bus Interrupt Channel B Control Registers Logic Am85C30 AMD of WR15 is set. 19 bit Frame Status FIFO. TxDA Baud Rate RxDA Transmitter Generator Receiver RTxCA TRxCA 10 19 Bit Frame ...
Page 10
... Miscellaneous transmitter/receiver control bits, data encoding WR11 Clock mode control, Rx and Tx clock source WR12 Lower byte of baud rate generator time constant WR13 Upper byte of baud rate generator time constant WR14 Miscellaneous control bits, DPLL control WR15 External/Status interrupt control Am85C30 of WR15 is 0 ...
Page 11
... Am85C30 AMD 11 ...
Page 12
... DMA control Parity Stop Data Data Asynchronous Data CRC Monosync Data CRC Bisync Data CRC External Sync Information CRC SDLC/HDLC 25 Figure 3. SCC Protocols Am85C30 and CCITT ( Marking Line CRC 1 2 CRC 1 2 CRC 1 2 Flag ...
Page 13
... EOP (End of Poll), around the loop. The EOP character is the bit pattern 11111110. Because of zero insertion during messages, this bit pat- tern is unique and easily recognized. Am85C30 AMD Data Data 10216F-8 ...
Page 14
... For FM encoding, the DPLL still counts from 0 to 31, but with a cycle corresponding to two bit times. When the DPLL is locked, the clock edges in the data stream should occur between counts 15 and 16 and between Am85C30 Error (0066) 0 (00CE) 0 (0113) 0 ...
Page 15
... However, transitions on these inputs can still cause in- terrupts. Local Loopback works in asynchronous, SYNC, and SDLC modes with NRZ, NRZI coding of the data stream Figure 6. Data Encoding Methods Am85C30 AMD WAIT/ transmitter interrupts and 0 Bit Cell Level High = 1 Low = 0 ...
Page 16
... CPU in one of three ways: Interrupt on First Receive Character or Special Receive condition Interrupt on all Receive Characters or Special Receive condition Interrupt on Special Receive condition only Peripheral INT INTACK IEO IEI AD – Figure 7. Z-Bus Interrupt Schedule Am85C30 Peripheral INT INTACK IEI AD – 10216F-11 ...
Page 17
... Read registers from which the system can read Status, Baud rate, or Interrupt information. On the Am85C30, only four data registers (Read and Write for Channels A and B) are directly selected by a High on the D/C input and the appropriate levels on the RD, WR, and A/B pins ...
Page 18
... Am85C30 Technical Manual for detailed descriptions of the read registers. Write Registers The ESCC contains 15 Write registers (16 counting WR8, the transmit buffer) in each channel. These Write registers are programmed separately to configure the functional “personality” of the channels. Two registers (WR2 and WR9) are shared by the two channels that can be accessed through either of them ...
Page 19
... Read Register Interrupt Vector* *FIFO Data Available Status **FIFO Overflow Status Am85C30 AMD Channel B EXT STAT IP* Channel B Tx IP* Channel B Rx IP* Channel A EXT STAT IP* Channel A Tx IP* Channel *Always Channel D ...
Page 20
... Enable Int on Next Rx Character Reset Tx Int Pending Error Reset Reset Highest IUS Figure 9. Write Register Bit Functions Am85C30 Upper Byte Time Constant ...
Page 21
... SYNC SYNC SYNC SYNC ADR ADR ADR ADR ADR Am85C30 AMD Write Register Parity Enable Parity Even/Odd Sync Modes Enable Stop Bit/Character 1/2 Stop Bits/Character ...
Page 22
... Receive Clock = RTxC Pin 0 0 Receive Clock = TRxC Pin Receive Clock = BR Generator Output 1 1 Receive Clock = DPLL Output Am85C30 Monosync 8 Bits SYNC SYNC 1 0 Monosync 8 Bits 1 1 Bisync 16 Bits SYNC SYNC 9 8 Bisync 12 Bits SYNC SYNC 5 ...
Page 23
... Set NRZI Mode Figure 9. Write Register Bit Functions (continued) Am85C30 Timing The ESCC generates internal control signals from WR and RD that are related to PCLK. Since PCLK has no phase relationship with WR and RD, the circuitry gener- ating these internal control signals must provide time for metastable conditions to disappear ...
Page 24
... SCC. In this case, the ESCC may be programmed to respond to RD Low by placing its inter- rupt vector rupt-Under-Service latch internally. Address Valid Data Valid Figure 10. Read Cycle Timing Address Valid Data Valid Figure 11. Write Cycle Timing Vector Am85C30 – then sets the appropriate Inter- 0 10216F-14 10216F-15 10216F-16 ...
Page 25
... FIFO FIFO Enhancements When used with a DMA controller, the Am85C30 Frame Status FIFO enhancement maximizes the ESCC’s abil- ity to receive high-speed back-to-back SDLC messages while minimizing frame overruns due to CPU latencies in responding to interrupts. Additional logic was added to the industry-standard ...
Page 26
... Internal Byte Strobe Increments Counter Reset Reset Byte Counter Byte Counter Load Counter Into FIFO and Increment PTR Figure 14. SDLC Byte Counting Detail Am85C30 Reset Byte Counter Load Counter Into FIFO and Increment PTR 10216F-18 ...
Page 27
... RR11, and WR7 is accessed by executing a read to RR14. The Am85C30 register map with bit D and bit D 6 deter both bits D WR7 is set to 1, then the Am85C30 register map is as determines 0 shown in Table 6. Am85C30 AMD 10216F-19 of WR15 is set to 1, two additional registers 2 of WR15 is set to 1 ...
Page 28
... Am85C30 6 Functions Enabled 10 19 bit FIFO enhancement enabled only SDLC/HDLC enhancements enabled only SDLC/HDLC enhancements enabled with extended read enabled 10 19 bit FIFO and SDLC/HDLC enhancements enabled 10 19 bit FIFO and SDLC/HDLC enhancements ...
Page 29
... Am85C30 AMD SDLC/HDLC SDLC/HDLC Auto Auto EOM Turnoff Tx Flag Reset Write Read WR0B RR0B WR1B RR1B WR2 RR2B WR3B RR3B WR4B RR4B (WR4B) WR5B ...
Page 30
... Am85C30 Write Read WR0B RR0B WR1B RR1B WR2 RR2B WR3B RR3B WR4B RR4B (WR4B) WR5B RR5B (WR5B) WR6B RR6B WR7B RR7B WR0A RR0A WR1A RR1A WR2 RR2A WR3A ...
Page 31
... FIFO. Thus, the received CRC characters are unavail- able for use. CMOS Am85C30 On the Am85C30, the option of being able to receive the 3 complete CRC characters generated by the transmitter is provided when both bit D are set to 1. When these 2 bits are set and an end-of- ...
Page 32
... Figure 17A. 5 Bits/Character Am85C30 Residue Code 012 101 ...
Page 33
... Am85C30 AMD ...
Page 34
... Figure 17C. 7 Bits/Character Am85C30 Residue Code 012 100 ...
Page 35
... Residue Code 012 101 (7 Residue Bits Am85C30 AMD ...
Page 36
... Low or High state as shown in Figure 18. of WR15 to 1 will 0 On the CMOS Am85C30, an option is provided that al- lows setting the TxD pin High when operating in SDLC mode with NRZI encoding enabled. If bit D set to 1, then bit D pin High. Note that the operation of this bit is independ- ent of the Tx Enable bit in WR5 ...
Page 37
... WR9 is set to 1. 2-Mb/s FM Data Transmission and Reception The 16-MHz version of the CMOS Am85C30 (Am85C30-16) is capable of transmitting and receiving FM-encoded data at the rate of 2 Mb/s. This is accom- plished by applying a 32-MHz clock to the RTxC pin and assigning this waveform to drive the Internal Digital Phase-Locked Loop (DPLL) clock. This feature allows ...
Page 38
... MHz output unloaded Unmeasured pins returned to ground = 1 MHz over specified temperature range into the referenced pin. Standard conditions are as follows: +4.5 V GND = From Output Under Test 10216F-23 Am85C30 ) . . . . . . . + – + ...
Page 39
... PCLK Setup Time NA to TxD Delay (Xl Mode) 200 to TxD Delay (Xl Mode) 200 200 150 50 150 50 488 125 125 1000 150 150 488 200 200 Am85C30 AMD 10 MHz 16.384 MHz Min Max Min Max Unit 150 80 ns 250 180 ...
Page 40
... W/REQ Wait 3 RTxC, TRxC Receive 4 RxD SYNC External TRxC RTxC Transmit TxD TRxC Output RTxC TRxC CTS, DCD, R1 SYNC Input 40 2.0 V 2.0 V Test Points 0 Figure 19. General Timing Am85C30 10216F- 10216F-26 ...
Page 41
... INT Valid Delay Parameter Description W/REQ Valid Delay to Wait Inactive Delay to SYNC Valid Delay to INT Valid Delay to W/REQ Valid Delay to Wait Inactive Delay to DTR/REQ Valid Delay to DTR/REQ Valid Delay to INT Valid Delay Am85C30 AMD 10 MHz 8.192 MHz Min Max Min Max Unit ...
Page 42
... Setup Time 145 Hold Time 0 Hold Time 40 Setup Time 0 Hold Time 0 Setup Time 60 Setup Time 0 Hold Time (Note1) 0 Setup Time 60 150 0 0 140 40 Am85C30 10 MHz 16.384 MHz Min Max Min Max Unit 40 2000 26 2000 ns 40 2000 26 2000 100 ...
Page 43
... RTxC TRxC Receive W/REQ Request W/REQ Wait SYNC Output INT RTxC TRxC Transmit W/REQ Request W/REQ Wait DTR REQ Request INT CTS, DCD, RI SYNC Input INT Figure 20. System Timing Am85C30 AMD 10216F-27 43 ...
Page 44
... – Read – Write W/REQ Wait W/REQ Request DTR/REQ Request INT Valid Valid Figure 21. Read and Write Timing Am85C30 10216F-28 ...
Page 45
... Hold Time 0 4.0TcPc to INT Valid Delay (Note 2) (Acknowledge) 150 150 (Acknowledge) Setup 95 (Acknowledge) Hold 0 to IEO Delay Delay for No Reset 15 Delay for No Reset 15 150 3.5 Am85C30 AMD 10 MHz 16.384 MHz Min Max Min Max 220 160 100 125 170 ...
Page 46
... AMD PCLK INTACK – IEI 43 IEO INT 46 47 Figure 22. Reset Timing 49 Figure 23. Cycle Timing Valid Figure 24. Interrupt Acknowledge Timing Am85C30 48 10216F-29 10216F- 10216F-31 ...
Page 47
... PCLK Setup Time NA to TxD Delay (Xl Mode) 200 to TxD Delay (Xl Mode) 200 200 150 50 150 50 488 125 125 1000 150 150 488 200 200 Am85C30 AMD 10 MHz 16.384 MHz Min Max Min Max Unit 150 80 ns 250 180 ...
Page 48
... INT Valid Delay Parameter Description W/REQ Valid Delay to Wait Inactive Delay to SYNC Valid Delay to INT Valid Delay to W/REQ Valid Delay to Wait Inactive Delay to DTR/REQ Valid Delay to DTR/REQ Valid Delay to INT Valid Delay Am85C30 10 MHz Max Min Max Unit TcPc TcPc 7 ...
Page 49
... Setup Time 145 Hold Time 0 Hold Time 40 Setup Time 0 Hold Time 0 Setup Time 60 Setup Time 0 Hold Time (Note1) 0 Setup Time 60 150 0 0 140 40 Am85C30 AMD 10 MHz 16.384 MHz Min Max Min Max Unit 40 1000 26 1000 ns 40 1000 26 1000 ...
Page 50
... Hold Time 0 4.0TcPc to INT Valid Delay (Note 2) (Acknowledge) 150 150 (Acknowledge) Setup 95 (Acknowledge) Hold 0 to IEO Delay Delay for No Reset 15 Delay for No Reset 15 150 3.5 Am85C30 10 MHz 16.384 MHz Min Max Min Max 220 160 100 125 170 100 ...
Page 51
... BSC is an ANSI standard for Basic Space Centering. 2.035 2.080 .100 BSC TOP VIEW .015 .022 SIDE VIEW Am85C30 AMD .098 MAX .565 .605 .005 MIN .590 .615 .008 .012 .015 .060 .150 MIN 0° ...
Page 52
... X 45 REF. (3x) (OPTIONAL) .640 .625 .660 BSC 52 .500 BSC .250 BSC .250 BSC .022 .028 .015 MIN .640 .660 .625 BSC INDEX CORNER .020 X 45 REF. (OPTIONAL) Am85C30 .500 BSC .054 .088 .064 .100 PLANE 2 PLANE 1 06825E AW 29 8/15/ ...
Page 53
... MIN TOP VIEW SIDE VIEW .050 REF .042 .056 .026 .032 .009 .650 .015 .656 .685 .695 TOP VIEW Am85C30 AMD .530 .580 .600 .625 .008 .015 .015 .060 0° 7° .630 06823E CJ76 PD 040 .700 1/21/ END VIEW ...
Page 54
... Add Am85C30-20 to valid combinations and - MHz to SPEED OPTION Page 5: Ordering Information, Industrial Products Add Am85C30-20 to valid combinations and - MHz to SPEED OPTION Change package description from “J = 44-Pin Leadless Chip Carrier (PL 044) ” to “J = 44-Pin Plastic Leaded Chip Carrier (PL 044) ”. ...
Page 55
... MHz Unmeasured pins returned to ground = 1 MHz over specified temperature range into the referenced pin. Standard conditions are as follows: +4.5 V GND = From Output Under Test 75 pF 10216F/1-1 Am85C30 ) . . . . . . . . . . + – + ...
Page 56
... Setup Time –200 Hold Time 5TcPc Setup Time NA 200 200 200 150 50 150 50 488 125 125 1000 150 150 488 200 200 Am85C30 AMD 10 MHz 16.384 MHz 20 MHz Min Max Min Max Min Max Unit 150 80 70 250 180 170 ...
Page 57
... RxD SYNC External TRxC RTxC Transmit TxD TRxC Output RTxC TRxC CTS, DCD, R1 SYNC Input 2.0 V 2.0 V Test Points 0 Figure 19. General Timing Am85C30 10216F/1 10216F/1-4 ...
Page 58
... SYNC Valid Delay 4 to INT Valid Delay 10 to W/REQ Valid Delay 5 to Wait Inactive Delay 5 to DTR/REQ Valid Delay 4 to DTR/REQ Valid Delay 5 to INT Valid Delay Am85C30 AMD 10 MHz Max Min Max Unit TcPc TcPc ...
Page 59
... Hold Time 0 Setup Time 145 Hold Time 0 Hold Time 40 Setup Time 0 Hold Time 0 Setup Time 60 Setup Time 0 0 Setup Time 60 150 0 0 140 40 Am85C30 10 MHz 16.384 MHz 20 MHz Min Max Min Max Min Max Unit 40 2000 26 2000 22 2000 40 2000 26 2000 22 2000 12 8 ...
Page 60
... RTxC TRxC Receive W/REQ Request W/REQ Wait SYNC Output INT RTxC TRxC Transmit W/REQ Request W/REQ Wait DTR REQ Request INT CTS, DCD, RI SYNC Input INT Figure 20. System Timing Am85C30 AMD 10216F/1-5 7 ...
Page 61
... D0–D7 Read 23 WR D0–D7 Write W/REQ Wait W/REQ Request DTR/REQ Request INT Valid Figure 21. Read and Write Timing Am85C30 Valid 30 36 10216F/1-6 ...
Page 62
... NA 500 (Acknowledge) 150 150 140 200 450 Delay for No Reset 15 Delay for No Reset 15 150 3.5 Am85C30 AMD 10 MHz 16.384 MHz 20 MHz Min Max Min Max Min Max Unit 160 100 90 125 100 ...
Page 63
... AMD PCLK INTACK 10 RD D0–D7 IEI 43 IEO INT Figure 22. Reset Timing Figure 23. Cycle Timing Figure 24. Interrupt Acknowledge Timing Am85C30 48 49 10216F/1 Valid 26 42 10216F/1-9 10216F/1-7 ...
Page 64
... Hold Time 5TcPc Setup Time NA 200 200 200 150 50 150 50 488 125 125 1000 150 150 488 200 200 Am85C30 AMD 20 MHz 10 MHz 16.384 MHz Industrial Only Min Max Min Max Min Max Unit 150 80 70 250 180 170 ...
Page 65
... SYNC Valid Delay 4 to INT Valid Delay 10 to W/REQ Valid Delay 5 to Wait Inactive Delay 5 to DTR/REQ Valid Delay 4 to DTR/REQ Valid Delay 5 to INT Valid Delay Am85C30 10 MHz Max Min Max Unit TcPc TcPc TcPc ...
Page 66
... Hold Time 0 Hold Time 40 30 Setup Time 0 0 Setup Time 60 50 Setup Time 0 0 Setup Time 60 50 150 125 0 0 140 40 Am85C30 AMD 20 MHz 10 MHz 16.384 MHz Industrial Only Max Unit Max Min Max Min 1000 26 1000 22 1000 1000 26 1000 22 1000 12 8 ...
Page 67
... NA 500 (Acknowledge) 150 150 140 200 450 Delay for No Reset 15 Delay for No Reset 15 150 3.5 Am85C30 20 MHz 10 MHz 16.384 MHz Industrial Only Min Max Min Max Min Max 160 100 90 125 100 ...
Page 68
... Am85C30 HARDWARE RESET IN SOFTWARE In the absence of a hardware logic or a Power-On-Reset mechanism, the following procedure should be used to ensure that the ESCC is properly reset. 1. Power Up 2. Read RR0 (Dummy Read) 3. Read RR1 (Dummy Read) 4. Write a C0h to WR9 (Hardware Reset) 5. Read RR0 ...