stac9708 ETC-unknow, stac9708 Datasheet
stac9708
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stac9708 Summary of contents
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... Integrating Mixed-Signal Solutions GENERAL DESCRIPTION: SigmaTel’s STAC9708/ general purpose 18-bit, full duplex, audio codec that conforms to the analog component specification of AC'97 (Audio Codec 97 Component Specification Rev. 2.1). The STAC9708/11 incorporates SigmaTel’s proprietary Sigma-Delta technology to achieve a DAC SNR in excess of 95dB. The DACs, ADCs, and mixer are integrated with analog I/Os, which include four analog line-level stereo inputs, two analog line-level mono inputs, two stereo outputs, and one mono output channel ...
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... ORDERING INFORMATION: PART PACKAGE NUMBER STAC9708T 48-pin TQFP 7mm x7mm x 1.4mm STAC9711T 48-pin TQFP 7mmx7mm x 1.4mm SigmaTel reserves the right to change specifications without notice. TEMPERATURE SUPPLY RANGE RANGE + DVdd = 3.3V or 5V, AVdd = + DVdd = 3.3V, AVdd = 3.3V 2 10/02/98 ...
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... Slot 2: Status Data Port 3.1.2.3 Slot 3: PCM Record Left Channel 3.1.2.4 Slot 4: PCM Record Right Channel 3.1.2.5 Slots 5-12: Reserved 3.2 AC-Link Low Power Mode 3.2.1 Waking up the AC-Link 4. STAC9708/11 Mixer 4.1 Mixer Input. 4.2 Mixer Output 4.3 PC Beep Implementations 4.4 Programming Registers 4.4.1 Reset Register 4.4.2 Play Master Volume Registers 4.4.3 PC Beep Register 4 ...
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... Signal Rise and Fall Times 42 9.6 AC-Link Low Power Mode Timing 43 9.7 ATE Test Mode 44 10. Electrical Specifications 45 10.1 Absolute Maximum Conditions 45 10.2 Recommended Operating Conditions 45 10.3 Power Consumption 46 10.4 AC-Link Static Digital Specifications 46 10.5 9708 Analog Performance Characteristics 47 10.6 9711 Analog Performance Characteristics 49 APPENDIX A 51 APPENDIX B 52 STAC9708/11 4 10/02/98 ...
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... Figure 8 – STAC9708 Audio Input Frame 29 Figure 9 – Start of an Audio Input Frame 30 Figure 10 – STAC9708 Powerdown Timing 31 Figure 11 – STAC9708 Mixer Functional Diagram 31 Figure 12 – Example of STAC9708 Powerdown/ Powerup flow 32 Figure 13 – STAC9708 Powerdown/Powerup 36 with analog still alive Figure 14 – Cold Reset 37 Figure 15 – ...
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... CD_L DVss2 CD_GND SDATA_IN 20 CD_R 9 DVdd2 21 MIC1 SYNC MIC2 RESET# 23 LINE_IN_L 12 PC_BEEP 24 LINE_IN_R # denotes active low STAC9708/11 Table 1. Package Dimensions KEY 9708/11 DIMENSION TQFP (lead width) 0. (pitch) 0.50 mm thickness 1.4 mm PIN SIGNAL PIN SIGNAL # NAME # NAME ...
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... STAC9708/11. Using this option with a STAC9704/07 as the primary codec, and the STAC9708 as the secondary codec, 6-channel output can be achieved in an AC'97 architecture. Also, the STAC9708/11 provides for a stereo enhancement feature, Sigmatel Surround 3D or SS3D. SS3D provides the listener with several options to expand the soundstage beyond the normal 2-speaker arrangement ...
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... AVss1 NOTE: Pins 31, 33, 34, 40 43, 44, and 48 are No Connects 8 STAC9708/11 Ferrite Bead * * Suggested ± 10uF 0.1uF 1 9 33pF ...
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... SigmaTel, Inc. Preliminary . 1 PIN/SIGNAL DESCRIPTIONS 1.1 Digital I/O These signals connect the STAC9708/11 to its AC'97 controller counterpart, an external crystal, multi- codec selection and external audio amplifier. Table 3. Digital Signal List SIGNAL NAME TYPE RESET # I XTL_IN I XTL_OUT O SYNC I BIT_CLK O SDATA_OUT I Serial, time division multiplexed, AC'97 input stream ...
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... SigmaTel, Inc. Preliminary 1.2 Analog I/O These signals connect the STAC9708/11 to analog sources and sinks, including microphones and speakers. Table 4. Analog Signal List SIGNAL NAME TYPE PC-BEEP I PHONE I From telephony subsystem speakerphone (or DLP - Down Line Phone) MIC1 I MIC2 I LINE-IN-L I LINE-IN-R I CD-L I CD-GND I CD-R I VIDEO-L ...
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... O CAP2 O CAP3 O APOP O EAPD O 11 STAC9708/11 Surround DAC Out Left Channel Surround DAC Out Right Channel DESCRIPTION Reference Voltage Anti-Aliasing Filter Cap - ADC channel Anti-Aliasing Filter Cap - ADC channel Analog Output Hold-Off Delay ADC reference Cap Anti-Pop Power Sustain Delay Anti-Pop Output Ground Shunt Control ...
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... DVss2 I Digital Gnd 2. AC-LINK Below is the figure of the AC-Link point to point serial interconnect between the STAC9708/11 and its companion controller. All digital audio streams and command/status information are communicated over this AC-Link. Please refer to the “Digital Interface” section 3 for details. ...
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... STAC9708/11 registers to their default states After signaling a reset to the STAC9708/11, the AC'97 controller should not attempt to play or capture audio data until it has sampled a “Codec Ready” indication via register 26h from the STAC9708/11. For proper reset operation SDATA_OUT should be “0” during “cold” reset. ...
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... If a slot is “tagged” invalid the responsibility of the source of the data, (STAC9708/11 for the input stream, AC'97 controller for the output stream), to stuff all bit positions with 0’s during that slot’s active time ...
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... If the “Valid Frame” bit this indicates that the current audio frame contains at least one slot time of valid data. The next 12 bit positions sampled by the STAC9708/11 indicate which of the corresponding 12 times slots contain valid data. In this way data streams of differing sample rates can be transmitted across AC-Link at its fixed 48kHz audio frame rate ...
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... Slot 1: Command Address Port The command port is used to control features, and monitor status (see Audio Input Frame Slots 1 and 2) of the STAC9708/11 functions including, but not limited to, mixer settings, and power management (refer to the control register section of this specification). The control interface architecture supports 16-bit read/write registers, addressable on even byte boundaries ...
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... Slot 6: PCM Center Channel Audio output frame slot 6 is the composite digital audio center stream used in a multi-channel application where the STAC9708/11 is programmed to accept the primary DAC PCM data from slots 6 and programming option, PCM data from slots 6 and 9 may be used to supply data to the surround DACs when slots 7 and 8 are used to drive the primary DACs ...
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... Audio output frame slot 7 is the composite digital audio left surround stream. In the default state, the STAC9708/11 accepts PCM data from slots 7 and 8 for the surround DACs, for output to the DAC_OUT pins programming option, PCM data from slots 7 and 8 may be used to supply data to the primary DACs when slots 6 and 9 are used to drive the surround DACs ...
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... Within slot 0 the first bit is a global bit (SDATA_IN slot 0, bit 15) which flags whether the STAC9708/ the "Codec Ready" state or not. If the “Codec Ready” bit this indicates that STAC9708/11 is not ready for normal operation. This condition is normal following the de-assertion of power on reset, for example, while STAC9708/11’ ...
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... SYNC. This falling edge marks the time when both sides of AC-Link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the STAC9708/11 transitions SDATA_IN into the first bit position of slot 0 ("Codec Ready" bit). Each new bit position is presented to AC-Link on a rising edge of BIT_CLK and subsequently sampled by the AC'97 controller on the following falling edge of BIT_CLK ...
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... Control Register Read Data Bit (3 :0) RESERVED If Slot 2 is tagged "invalid" by STAC9708/11, then the entire slot will be stuffed with 0's. 3.1.2.3 Slot 3: PCM Record Left Channel Audio input frame slot 3 is the left channel output of STAC9708/11 input MUX, post-ADC. STAC9708/11 ADCs are implemented to support 18-bit resolution. ...
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... Waking up the AC-Link Once the STAC9708/11 has halted BIT_CLK, there are only two ways to “wake up” the AC-Link. Both methods must be activated by the AC'97 controller. The AC-Link protocol provides for a “Cold AC'97 Reset”, and a “Warm AC'97 Reset”. The current power down state would ultimately dictate which form of reset is appropriate. Unless a “ ...
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... BIT_CLK, SYNC is treated as an asynchronous input used in the generation of a warm reset to the STAC9708/11. 4. STAC9708/11 MIXER The STAC9708/11 mixer is designed to the AC'97 specification to manage the playback and record of all digital and analog audio sources in the PC environment. These include: System Audio: digital PCM input and output for business, games and multimedia ...
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... DAC_OUT surround stereo DAC output MONO_OUT mic or mix for speakerphone or DLP out PCM in digital audio input to AC'97 Controller 24 STAC9708/11 CONNECTION from PC beeper output from telephony subsystem from mic jack from second mic jack from line-in jack cable from CD-ROM ...
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... Preliminary 4.1 Mixer Input The mixer provides recording and playback of any audio sources or output mix of all sources. The STAC9708/11 supports the following input sources: any mono or stereo source mono or stereo mix of all sources 2-channel input w/mono output reference (mic + stereo mix) Note: any unused input pins should have a capacitor (1 uF suggested) to ground. ...
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... PC_BEEP default to 0000h, mute off optional bits D13 register 02h register 06h are set to 1, then the corresponding attenuation is set to 46dB and the register reads will produce 1Fh as a value for this attenuation/gain block. 26 STAC9708/ ...
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... PC_BEEP signal needs to reach the output jack at all times. NOTE: the PC_BEEP is recommended to be routed to L & R Line outputs even when the STAC9708/ RESET state. This is so that Power On Self Test (POST) codes can be heard by the user in case of a hardware problem with the PC. ...
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... Record Select Control Register (Index 1Ah Used to select the record source independently for right and left. The default value is 0000h, which corresponds to Mic in. 28 STAC9708/11 FUNCTION 0 dB Attenuation 45 dB Attenuation dB Attenuation FUNCTION +12 dB gain 0 dB gain -34.5 dB gain - dB gain ...
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... SL2…SL0 LEFT RECORD SOURCE STAC9708/11 Mic CD In (right) Video In (right) Aux In (right) Line In (right) Stereo Mix (right) Mono Mix Phone Mic CD In (L) Video In (L) Aux In (L) Line In (L) Stereo Mix (L) Mono Mix Phone ...
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... This register is used to control the 3D stereo enhancement function, Sigmatel Surround 3D (SS3D), built into the AC'97 component. Note that register bits, DP1-DP0 and DPR1-DPR0 are used to control the separation ratios in the 3D control for both LINE_OUT and DAC_OUT respectively. This allows 30 STAC9708/11 FUNCTION +22.5 dB gain 0 dB gain ...
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... LSBs are used (MC0 and MC1), and they define which AC-Link slot data is supplied to the four audio DACs on the STAC9708/11. PCM2 in the table below is the surround stereo DAC, which drives the DAC_OUT pins. The purpose of using slot 10 and 11 in the final configuration is to allow the possibility of an eight channel architecture using two STAC9708 devices in the multi-codec configuration. Also see “ ...
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... EAPD External Amplifier Power Down REF VREF’ nominal level ANL Analog mixers, etc. ready DAC DAC section ready to playback data ADC ADC section ready to playback data 32 STAC9708/11 PCM OUT PCM2 PCM2 RIGHT LEFT RIGHT Slot 4 Slot 7 Slot 8 Slot 8 Slot 6 ...
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... The Analog Special Register has two read/write bits used to control two functions specific to the STAC9708. DAC –6dB is used to program the DAC outputs to a –6dB signal level relative to the value of gain already programmed. Similarly, ADC –6dB attenuates any signal input to the ADC by 6dB. This second function is very useful in applications with greater than 1Vrms input levels the case with many CDROMs ...
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... LOW POWER MODES The STAC9708/11 is capable of operating at reduced power when no activity is required. The state of power down is controlled by the Powerdown Register (26h). There are 7 commands of separate power down. The power down options are listed in Table 18. The first three bits , PR0..PR2, can be used individually or in combination with each other, and control power distribution to the ADC’ ...
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... This will restart the AC-Link (resetting PR4 to zero). The STAC9708/11 can also be woken up with a cold reset. A cold reset will reset all of the registers to their default states. When a section is powered back on, the Powerdown Control/Status register (index 26h) should be read to verify that the section is ready (stable) before attempting any operation that requires it ...
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... Secondary Codec Operation When the STAC9708/11 is configured as a Secondary device the BIT_CLK pin is configured as an input at power up. Using the BIT_CLK provided by the Primary Codec insures that everything on the AC-Link will be synchronous Secondary device it can be defined as Codec ID 01, 10 the two-bit field(s) of the Extended Audio and/or Extended Modem ID Register(s) ...
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... New definitions for Secondary Codec Register Access 7. TESTABILITY The STAC9708/11 has two test modes. One is for ATE in-circuit test and the other is restricted for SigmaTel’s internal use. STAC9708/11 enters the ATE in circuit test mode if SDATA_OUT is sampled high at the trailing edge of RESET# ...
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... EXTENDED CODEC FUNCTIONALITY 8.1 Anti-Pop Circuitry The STAC9708/11 provides an integrated output signal (APOP on pin 34) to aid in low-component-count anti- pop implementations. An audible speaker "pop" can occur when the main power is applied to, or removed from, the codec or audio output amplifier coupled systems, the speaker sided of the ac coupling capacitor is shunted to ground through a transistor or FET ...
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... SigmaTel, Inc. Preliminary 9.2 Warm Reset Figure 15. Warm Reset SYNC BIT_CLK Table 24. Warm Reset PARAMETER SYNC active high pulse width SYNC inactive to BIT_CLK startup delay 39 STAC9708/11 Tsync_high Tsync_2clk SYMBOL MIN TYP MAX UNITS Tsync_high - 1 Tsync2clk 162 10/02/98 ...
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... BLT_CLK high pulsewidth (note 1) Tclk_high BIT_CLK low pulse width (note 1) Tclk_low SYNC frequency SYNC period Tsync_period SYNC high pulse width Tsync_high SYNC low_pulse width Tsync_low Notes: 1) Worst case duty cycle restricted to 40/60. 40 STAC9708/11 Tclk_low Tsync_low Tsync_period MIN TYP MAX UNITS - 12.288 - MHz - 81 ...
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... SDATA_OUT Thold SYNC Table 26. Data Setup and Hold PARAMETER SYMBOL Setup to falling edge of BIT_CLK Hold from falling edge of BIT_CLK Note 1: Setup and hold time parameters for SDATA_IN are with respect to the AC'97 controller. 41 STAC9708/11 Tsetup Thold Tsetup MIN TYP MAX UNITS Tsetup 15.0 ...
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... Figure 18. Signal Rise and Fall Times BIT_CLK Triseclk SDATA_IN Trisedin Table 27. Signal Rise and Fall Times PARAMETER SYMBOL BIT_CLK rise time Triseclk BIT_CLK fall time Tfallclk SDATA_IN rise time Trisedin SDATA_IN fall time Tfalldin 42 STAC9708/11 Tfallclk Tfalldin MIN TYP MAX UNITS ...
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... Figure 19. AC-Link Low Power Mode Timing Slot 1 SYNC BIT_CLK Write to SDATA_OUT 0x20 SDATA_IN Note: BIT_CLK not to scale Table 28. AC-Link Low Power Mode Timing PARAMETER End of Slot 2 to BIT_CLK, SDATA_IN low 43 STAC9708/11 Slot 2 Data Don't care PR4 Ts2_pdown SYMBOL MIN TYP MAX UNITS Ts2_pdown - - 1 ...
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... SDATA_OUT high for the trailing edge of RESET# causes STAC9708/11’s AC-Link outputs to go high impedance which is suitable for ATE in circuit testing. 2. Once either of the two test modes have been entered, the STAC9708/11 must be issued another RESET# with all AC-Link signals low to return to the normal operating mode. # denotes active low. ...
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... PARAMETER Power Supplies + 3.3V Digital + 5V Digital + 5V Analog + 3.3V Analog Ambient Temperature SigmaTel reserves the right to change specifications without notice. 45 STAC9708/11 Vss - 0.3V TO Vdd + 0. - +125 o C 260 o C FOR 10 SECONDS ± except Vrefout = ± 5mA MIN TYP MAX UNITS 3 ...
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... Input Voltage Range Low level input range High level input voltage High level output voltage Low level output voltage Input Leakage Current (AC-Link inputs) Output Leakage Current (Hi-Z’d AC-Link outputs) Output buffer drive current 46 STAC9708/11 MIN TYP MAX UNITS ...
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... SigmaTel, Inc. Preliminary 10.5 STAC9708 Analog Performance Characteristics DVdd = 3.3V ± 5%, AVss=DVss=0V; 1 kHz input sine wave; Sample Frequency = 48 kHz Vrms, 10K /50pF load, Testbench Characterization BW – 20 kHz settings on all gain stages) Table 33. Analog Performance Characteristics PARAMETER MIN Full Scale Input Voltage: ...
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... Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible noise. 7. The integrated Out-of-Band noise generated by the DAC process, during normal PCM audio playback, over a bandwidth 28.8 to 100 kHz, with respect Vrms DAC output. 48 STAC9708/11 0 0.5 dB 100 ppm/deg ...
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... Total Harmonic Distortion: 4 Line Output 5 D/A & A/D Frequency Response Transition Band Stop Band 6 Stop Band Rejection 7 Out-of-Band Rejection Group Delay Power Supply Rejection Ratio (1kHz) Crosstalk between Input channels 49 STAC9708/ AVdd = DVdd = (T ambient MIN TYP MAX UNITS - 0.5 - Vrms 0.5 Vrms 0.5 Vrms ...
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... Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible noise. 7. The integrated Out-of-Band noise generated by the DAC process, during normal PCM audio playback, over a bandwidth 28.8 to 100 kHz, with respect Vrms DAC output. 50 STAC9708/11 - +100 ...
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... Appendix A SPLIT INDEPENDENT POWER SUPPLY OPERATION In PC applications, one power supply input to the STAC9708/11 may be derived from a supply regulator (as shown in Figure 3) and the other directly from the PCI power supply bus. When power is applied to the PC, the regulated supply input to the IC will be applied some time delay after the PCI power supply. Without proper on- chip partitioning of the analog and digital circuitry, some manufacturer's codecs would be subject to on-chip SCR type latch-up ...
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... Appendix B +5.0V/+3.3V POWER SUPPLY OPERATION NOTES The STAC9708 is capable of operating from a single 5V supply connected to both DVdd and AVdd. Even though the STAC9708 has digital switching levels of 0.2Vdd to 0.5Vdd (See AC Link Electrical Characteristics in this data book), we recommend that all digital interface signals to the AC-Link be 5V. If digital interface signals below 5V are used, then appropriate level shifting circuitry must be provided to ensure adequate digital noise immunity ...
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... SigmaTel, Inc. Preliminary - NOTES - 53 STAC9708/11 10/02/98 ...
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... SigmaTel, Inc. Preliminary - NOTES - 54 STAC9708/11 10/02/98 ...
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... SigmaTel, Inc. Preliminary - NOTES - 55 STAC9708/11 10/02/98 ...
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... SigmaTel, Inc. Preliminary For more information, please contact: SigmaTel, Inc. 6101 W. Courtyard Dr., Bldg. 1, Suite 100 Austin, Texas 78730 Tel (512) 343-6636, Fax (512) 343-6199 email: sales@sigmatel.com Homepage: 56 STAC9708/11 www.sigmatel.com 10/02/98 ...