hip0063 Intersil Corporation, hip0063 Datasheet
hip0063
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hip0063 Summary of contents
Page 1
... The HIP0063 has an internal drain-to-gate zener which is used to voltage clamp the output drain-to-source voltage of the MOSFET. The HIP0063 is fabricated in a Power BiMOS IC process, and is intended for use in automotive and other applications having a wide range of temperature o ...
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... HLOS (SEL) HPW01 HLOS HPW45 HARDWARE GENERATED OR CUSTOM LOGIC SOURCED PWM CONTROL SIGNAL INPUTS FIGURE 1. TYPICAL APPLICATION CIRCUIT FOR THE HIP0063 SHOWING HOW THE GATE DRIVE OUTPUT AND DRAIN MONITOR INPUT CONTROLS TWO HIP0061 THREE FET ARRAYS CS SCK (CPOL = 0, CPHA = 1) xxxxxx xxxxxx FIGURE 2 ...
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... Threshold Voltge at Rising Edge, PI0-5, HLOS, HPW01, HPW45 Input Hysteresis Voltage; PI0-5, HLOS, HPW01, HPW45 Input Capacitance, SCK, SI DATA OUTPUT SO Data Output High Voltage SO Data Output Low Voltage SO Three-State Leakage Current SO Three-State Capacitance Specifications HIP0063 Thermal Information Thermal Resistance 28 Lead SOIC Package . . . . . . . . . . . . . . . . . . . . . . . + 0. 0. ...
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... HARDWARE GENERATED PWM INPUT FIGURE 3. TYPICAL APPLICATION CIRCUIT FOR THE HIP0063 SHOWING THE V TECTION COMPONENTS. FOR THE VALUES SHOWN, GIVEN A LOAD DUMP OF 80V THAT DECAYS TO THE V LEVEL IN 350ms, THE 27V ZENER DIODE IS REQUIRED TO CLAMP THE TRANSIENT TO 60V MAXIMUM. FOR THE REVERSE BATTERY PROTECTION, THE ZENER DIODE CLAMPS NEGATIVE VOLTAGES Specifi ...
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... Rising Edge of SCK to SO (Data Valid LEAD SCK t VALID SI (MSB = 0) LAST BIT SO XMITTED t SOEN FIGURE 4. TIMING DIAGRAM FOR THE HIP0063 SHOWING THE SPI BUS INPUT CONTROL SIGNALS Specifications HIP0063 (See Figure 4) SYMBOL TEST CONDITION 200pF SCK L t SCK = 0.8V to 0.8V SCK t SCK = ...
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... Detailed information on the bit structure for both 8-bit and 16-bit operation is shown in Table 1. A special feature of the HIP0063 is a PWM mode of operation set by a high on the HLOS pin. This mode is primarily used to control fuel injectors and allows direct access to control chan- nels 0 and 1 from the HPW01 Pin and channels 4 and 5 from the HPW45 Pin ...
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... Threshold, the POR forces a reset which turns-off the Gate Drive outputs Battery Voltage Level Power Supply Monitor Pin PWR All MOSFETs are normally controlled by the HIP0063 and are separately biased by a Battery or System level power supply. The V pin monitors the Battery/System Power Supply and PWR forces over-voltage shutdown under excessive high voltage conditions by forcing all Gate Drive outputs low ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com HIP0063 M28.3 (JEDEC MS-013-AE ISSUE C) ...