am41dl6408g Meet Spansion Inc., am41dl6408g Datasheet
am41dl6408g
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am41dl6408g Summary of contents
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... Am41DL6408G Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to customers of both AMD and Fujitsu ...
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... PRELIMINARY Am41DL6408G Stacked Multi-Chip Package (MCP) Flash Memory and SRAM 64 Megabit ( 8-Bit 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit ( 8-Bit/512 K x 16-Bit) Static RAM DISTINCTIVE CHARACTERISTICS MCP Features Power supply voltage of 2.7 to 3.3 volt High performance — Access time as fast Flash/55 ns SRAM Package — ...
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... The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly re- duced in both modes. Am41DL6408G August 19, 2002 ...
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... Figure 25. Temporary Sector Unprotect Timing Diagram .............. 50 Figure 26. Sector/Sector Block Protect and Unprotect Timing Diagram ............................................................. 51 Alternate CE#f Controlled Erase and Program Operations .... 52 Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings.......................................................................... 53 SRAM Read Cycle .................................................................. 54 Figure 28. SRAM Read Cycle—Address Controlled...................... 54 Figure 29. SRAM Read Cycle ........................................................ 55 Am41DL6408G vs. Frequency ............................................ 39 3 ...
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... Package Pin Capacitance . . . . . . . . . . . . . . . . . . 59 Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . SRAM Data Retention . . . . . . . . . . . . . . . . . . . . . 60 Figure 33. CE1#s Controlled Data Retention Mode....................... 60 Figure 34. CE2s Controlled Data Retention Mode......................... 60 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 61 FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm ............. 61 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 62 Am41DL6408G August 19, 2002 ...
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... August 19, 2002 Am41DL6408G Flash Memory 70 RY/BY# 64 MBit Flash Memory DQ15 to DQ0 V s CCQ SS SSQ 8 MBit DQ15 to DQ0 Static RAM Am41DL6408G SRAM DQ15/A–1 to DQ0 5 ...
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... CE# COMMAND REGISTER BYTE# WP#/ACC DQ15–DQ0 A21–A0 Mux OE# BYTE# Bank 1 Bank 1 Address X-Decoder Bank 2 Address Bank 2 X-Decoder Status Control X-Decoder Bank 3 Bank 3 Address X-Decoder Bank 4 Address Bank 4 Am41DL6408G DQ15–DQ0 Mux August 19, 2002 ...
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... DQ14 Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150 C for prolonged periods of time. Am41DL6408G Flash only A10 NC SRAM only B10 NC Shared D9 A15 ...
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... SRAM Power Supply Device Ground (Common Pin Not Connected Internally LOGIC SYMBOL 19 A18–A0 A21–A19, A-1 SA CE#f CE1#s CE2s OE# WE# WP#/ACC RESET# UB#s LB#s CIOf CIOs Am41DL6408G DQ15–DQ0 RY/BY# August 19, 2002 ...
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... The state machine outputs dictate the function of the device. Tables 1-3 lists the device bus operations, the inputs and control levels they require, and the result- ing output. The following subsections describe each of these operations in further detail. Am41DL6408G Valid Combinations Package Marking T, S M41000000G ...
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... Don’t Care SRAM Address Address In Data In and CE2s = V at the same time. IH the boot sectors protection will be removed. IH Am41DL6408G ; SRAM Word Mode, CIOs = WP#/ACC DQ7– DQ15– (Note 4) DQ0 X H L/H D OUT ...
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... 9.0 ± 0 Don’t Care SRAM Address Address In Data In and CE2s = V at the same time. IH the boot sectors protection will be removed. IH Am41DL6408G ; SRAM Byte Mode, CIOs = UB#s WP#/ACC DQ7– RESET# (Note 3) (Note 4) DQ0 X H L/H ...
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... 9.0 ± 0 Don’t Care SRAM Address Address In (for Flash Byte Mode, DQ15 = A-1 and CE2s = V at the same time. IH the boot sectors protection will be removed. IH Am41DL6408G ; SRAM Word Mode, CIOs = UB#s WP#/ACC DQ7– RESET# (Note 4) DQ0 X H ...
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... CE#f and OE# pins to V control and selects the device. OE# is the output con- trol and gates array data to the output pins. WE# should remain at V whether the device outputs array data in words or bytes. Am41DL6408G ; SRAM Byte Mode, CIOs = UB#s WP#/ACC DQ7– ...
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... CC mode, but the standby current will be greater. The de- vice requires standard access time (t cess when the device is in either of these standby modes, before it is ready to read data. Am41DL6408G on this pin, the device auto- HH must not be asserted the table represent the cur- CC7 ± ...
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... Am41DL6408G ±0.3 V, the device SS f). If RESET# is CC4 ±0.3 V, the standby cur- SS (not during Embedded READY after the output from the device is IH (x16) Address Range 00000h– ...
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... Am41DL6408G (x16) Address Range 80000h–87FFFh 88000h–8FFFFh 90000h–97FFFh 98000h–9FFFFh A0000h–A7FFFh A8000h–AFFFFh B0000h–B7FFFh B8000h–BFFFFh C0000h–C7FFFh C8000h–CFFFFh D0000h–D7FFFh D8000h–DFFFFh E0000h– ...
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... Am41DL6408G (x16) Address Range 200000h–207FFFh 208000h–20FFFFh 210000h–217FFFh 218000h–21FFFFh 220000h–227FFFh 228000h–22FFFFh 230000h–237FFFh 238000h–23FFFFh 240000h–247FFFh 248000h–24FFFFh 250000h–257FFFh 258000h–25FFFFh 260000h– ...
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... Table 6. Bank Address A21–A19 001, 010, 011 100, 101, 110 Table 7. SecSi Sector Addresses Sector Size 256 bytes 000000h–0000FFh Am41DL6408G (x16) Address Range 380000h–387FFFh 388000h–38FFFFh 390000h–397FFFh 398000h–39FFFFh 3A0000h–3A7FFFh 3A8000h–3AFFFFh 3B0000h–3B7FFFh 3B8000h–3BFFFFh 3C0000h– ...
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... To change 256 (4x64) Kbytes data in protected sectors efficiently, the temporary 256 (4x64) Kbytes sector unprotect function is available. See “Temporary 256 (4x64) Kbytes Sector Unprotect”. Am41DL6408G Sector/ A21–A12 Sector Block Size 01110XXXXX 256 (4x64) Kbytes 01111XXXXX ...
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... Notes: 1. All protected sectors unprotected (If WP#/ACC = V sectors 0, 1, 140, and 141 will remain protected). 2. All previously protected sectors are protected once again. Figure 1. Temporary Sector Unprotect Operation Am41DL6408G V . During this mode, formerly protected ID is removed from the RE sectors 0, 1, 140, and ...
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... Reset PLSCNT = 1 Increment PLSCNT No Yes PLSCNT = 1000? Yes Device failed Sector Unprotect Algorithm Am41DL6408G START PLSCNT = 1 RESET Wait First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes No All sectors protected? Yes ...
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... V and power-down transitions, or from system noise. Low V Write Inhibit CC When V is less than V CC cept any write cycles. This protects data during V Am41DL6408G This IH ID power- the device does not ac- LKO CC ...
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... Query Unique ASCII string “QRY” 0059h 0002h Primary OEM Command Set 0000h 0040h Address for Primary Extended Table 0000h 0000h Alternate OEM Command Set (00h = none exists) 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists) 0000h Am41DL6408G Description 23 ...
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... Erase Block Region 3 Information 0020h (refer to the CFI specification or CFI publication 100) 0000h 0000h 0000h Erase Block Region 4 Information 0000h (refer to the CFI specification or CFI publication 100) 0000h Am41DL6408G Description pin present) PP pin present µs N µ s (00h = not supported) ...
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... Not supported Supported Bank Organization 0004h 00 = Data at 4Ah is zero Number of Banks Bank 1 Region Information 0017h X = Number of Sectors in Bank 1 Bank 2 Region Information 0030h X = Number of Sectors in Bank 2 Bank 3 Region Information 0030h X = Number of Sectors in Bank 3 Bank 4 Region Information 0017h X = Number of Sectors in Bank 4 Am41DL6408G Description 25 ...
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... The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system is- sues the four-cycle Exit SecSi Sector command se- Am41DL6408G August 19, 2002 ...
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... In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 3 illustrates the algorithm for the program oper- ation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 18 for timing diagrams. Am41DL6408G any operation HH 27 ...
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... Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can de- termine the status of the erase operation by reading Am41DL6408G August 19, 2002 ...
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... Command Sequence (Notes 1, 2) Data Poll to Erasing Bank from System No Data = FFh? Erasure Completed Notes: 1. See Table 14 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer. Figure 4. Erase Operation Am41DL6408G START Embedded Erase algorithm in progress Yes 29 ...
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... The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 16. Command is valid when device is ready to read array data or when device is in autoselect mode. Am41DL6408G Fourth Fifth Sixth Addr Data ...
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... During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Figure 5. Data# Polling Algorithm Am41DL6408G Yes No Yes Yes No ...
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... Reset Command Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information. Figure 6. Toggle Bit Algorithm Am41DL6408G No Yes Yes No Yes ...
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... DQ3 prior to and following each subsequent sector erase com- mand. If DQ3 is high on the second status check, the last command might not have been accepted. Table 15 shows the status of DQ3 relative to the other status bits. Am41DL6408G 33 ...
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... The device outputs array data if the system addresses a non-busy bank Table 15. Write Operation Status DQ7 DQ5 (Note 2) DQ6 (Note 1) DQ7# Toggle 0 Toggle 1 No toggle Data Data Data DQ7# Toggle Am41DL6408G DQ2 DQ3 (Note 2) RY/BY# 0 N/A No toggle Toggle 0 0 N/A Toggle 1 Data Data 1 ...
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... Operating ranges define those limits between which the functionality of the device is guaranteed. August 19, 2002 +0.8 V –0.5 V –2 Figure 7. Maximum Negative Overshoot Waveform + –2 2.0 V Figure 8. Maximum Positive Overshoot Waveform Am41DL6408G ...
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... ACC pin CE OE pin 4.0 mA min I = –2.0 mA min I = –100 µ min Am41DL6408G Min Typ Max Unit 1.0 µA 35 µA 1.0 µA 35 µ 0.2 5 µA 0.2 5 µA 0.2 5 µ ...
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... Embedded Erase or Embedded Program is in progress Automatic sleep mode enables the low power mode when addresses remain stable for t 200 nA. 5. Not 100% tested. August 19, 2002 max Am41DL6408G + 30 ns. Typical sleep mode current is ACC 37 ...
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... I = –1 CE1 CE2 = V , Other IH IL inputs = CE1#s V – 0.2 V, CE2 V – 0.2 V (CE1#s controlled) or CE2 0.2 V (CE2s controlled), CIOs = Other input = Am41DL6408G Min Typ Max Unit –1.0 1.0 µA –1.0 1.0 µ 0.4 V 2 µA August 19, 2002 ...
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... Figure 9. I Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 Note August 19, 2002 1500 2000 2500 Time Frequency in MHz Figure 10. Typical I vs. Frequency CC1 Am41DL6408G 3000 3500 4000 3 ...
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... Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels INPUTS Steady Changing from Changing from Does Not Apply Center Line is High Impedance State (High Z) Measurement Level Am41DL6408G 70, 85 Unit 1 TTL gate 0.0–3 ...
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... AC CHARACTERISTICS SRAM CE#s Timing Parameter JEDEC Std Description — t CE#s Recover Time CCR CE#f CE1#s CE2s Figure 13. Timing Diagram for Alternating Between SRAM to Flash August 19, 2002 Test Setup — t CCR t CCR Am41DL6408G All Speeds Unit Min CCR t CCR 41 ...
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... Test Setup CE# Read Toggle and Data# Polling Addresses Stable t ACC OEH t CE HIGH Z Output Valid Figure 14. Read Operation Timings Am41DL6408G Speed 70 Unit Min 70 85 Max Max Max 30 40 Max 30 35 Max 30 ...
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... RESET# August 19, 2002 Description Max Max Min Min Min Min Ready Reset Timings during Embedded Algorithms t Ready t RP Figure 15. Reset Timings Am41DL6408G All Speed Options Unit 20 s 500 ns 500 ...
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... Data Output (DQ7–DQ0) Address DQ15 Input Output t FHQV The falling edge of the last WE# signal t SET ( HOLD AH and t specifications Am41DL6408G Speed 70 Unit Data Output (DQ7–DQ0) Address Input Data Output (DQ14–DQ0) August 19, 2002 ...
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... Write Recovery Time from RY/BY Program/Erase Valid to RY/BY# Delay BUSY Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information. August 19, 2002 Byte Word Am41DL6408G Speed 70 Unit Min Min 0 ns ...
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... WPH A0h t BUSY is the true data at the program address. OUT Figure 18. Program Operation Timings Am41DL6408G Read Status Data (last two cycles WHWH1 D Status OUT VHH August 19, 2002 ...
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... These waveforms are for the word mode. Figure 20. Chip/Sector Erase Operation Timings August 19, 2002 SADD 555h for chip erase WPH t DH 30h 10 for Chip Erase t BUSY Am41DL6408G Read Status Data WHWH2 In Complete Progress ...
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... OEH GHWL Valid Out t SR/W Read Cycle Complement Complement Status Data Status Data Am41DL6408G Valid PA Valid PA t CPH t CP Valid Valid In In CE#f Controlled Write Cycles VA High Z Valid Data True High Z True Valid Data August 19, 2002 ...
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... AHT AS t AHT t ASO t CEPH t OEPH t OE Valid Valid Status Status (first read) (second read) Enter Erase Suspend Program Erase Erase Suspend Suspend Read Program Figure 24. DQ2 vs. DQ6 Am41DL6408G Valid Valid Data Status (stops toggling) Erase Resume Erase Erase Complete Read 49 ...
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... VIDR CE#f WE# RY/BY# Figure 25. Temporary Sector Unprotect Timing Diagram Min Min Min Min Program or Erase Command Sequence t RSP Am41DL6408G All Speed Options Unit 500 ns 250 VIDR ...
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... For sector protect For sector unprotect SADD = Sector Address. Figure 26. Sector/Sector Block Protect and August 19, 2002 Valid* Valid* 60h Sector/Sector Block Protect: 150 µs, Sector/Sector Block Unprotect Unprotect Timing Diagram Am41DL6408G Valid* Verify 40h Status 51 ...
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... Word or Byte (Note Sector Erase Operation (Note 2) WHWH2 WHWH2 Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information Byte Word Am41DL6408G Speed 70 Unit Min Min 0 ns Min ...
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... SADD for sector erase 555 for chip erase Data# Polling GHEL t t WHWH1 CPH t BUSY for program PD for program 55 for erase 30 for sector erase 10 for chip erase is the data written to the device. OUT Am41DL6408G PA DQ7# D OUT 53 ...
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... Figure 28. SRAM Read Cycle—Address Controlled Min Max Max Max Max Min Min Min Max Max Max Min UB#s and/or LB Am41DL6408G Speed Unit ...
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... At any given temperature and voltage condition, t interconnection. August 19, 2002 CO1 t CO2 OLZ t BLZ t LZ Data Valid Figure 29. SRAM Read Cycle (Max.) is less than t (Min.) both for a given device and from device to device HZ LZ Am41DL6408G OHZ 55 ...
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... Note (See Note (See Note 3) High-Z t WHZ applied in case a write ends as CE1#s or WE# going high low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when Am41DL6408G Speed Unit ...
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... (See Note 5) High-Z applied in case a write ends as CE1#s or WE# going high low CE1#s and low WE#. A write begins when CE1#s goes low and WE# goes low Am41DL6408G t (See Note Data Valid High-Z is measured from the beginning of write ...
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... Note 4) WP (See Note High-Z applied in case a write ends as CE1#s or WE# going high low CE#1s and low WE#. A write begins when CE1#s goes low and WE# goes low Am41DL6408G t (See Note Data Valid High-Z is measured from the beginning of write ...
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... V, 1,000,000 cycles. CC –100 mA = 3.0 V, one pin at a time. CC Test Setup OUT Test Conditions Am41DL6408G Unit Comments sec Excludes 00h programming prior to erasure (Note 4) sec µs µs Excludes system level µs overhead (Note 5) sec , 1,000,000 cycles. Additionally, CC Min Max – ...
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... V – 0.2 V (Note 3.0 V, CE1#s V – 0 (Note 1) See data retention waveforms 0.2 V (CE2s controlled), CIOs = V Data Retention Mode t SDR CE1 0 Data Retention Mode t SDR CE2s < 0.2 V Am41DL6408G Min Typ Max Unit 1.5 3.3 V 1.0 15 µA (Note RDR ...
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... PHYSICAL DIMENSIONS FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm August 19, 2002 Am41DL6408G 61 ...
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... Changed typical and maximum specifications for sec- tor erase time. Changed typical specification of chip erase. Revision B (August 19, 2002) Global Added 55 ns SRAM speed grade. MCP Block Diagram Removed A-1 from DQ15/A-1 input to Flash Memory and SRAM Am41DL6408G . ID for 85 ns SRAM and t . WHWH1 ...