am41pds3228d Meet Spansion Inc., am41pds3228d Datasheet

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am41pds3228d

Manufacturer Part Number
am41pds3228d
Description
32 Mbit 2 M ? 16-bit Cmos 1.8 Volt-only, Simultaneous Operation Page Mode Flash Memory And 8 Mbit 1 M ? 8-bit/512 K ? 16-bit Static Ram Preliminary
Manufacturer
Meet Spansion Inc.
Datasheet
Am41PDS3228D
Data Sheet
Continuity of Specifications
Continuity of Ordering Part Numbers
For More Information
Publication Number 26014 Revision A
Amendment +1 Issue Date May 13, 2003

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am41pds3228d Summary of contents

Page 1

... Am41PDS3228D Data Sheet Continuity of Specifications Continuity of Ordering Part Numbers For More Information Publication Number 26014 Revision A Amendment +1 Issue Date May 13, 2003 ...

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... PRELIMINARY Am41PDS3228D Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29PDS322D 32 Megabit ( 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation, Page Mode Flash Memory and 8 Mbit ( 8-Bit/512 K x 16-Bit) Static RAM DISTINCTIVE CHARACTERISTICS MCP Features Power supply voltage of 1.8 to 2.2 volt High performance — ...

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... The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode system can also place the de vice into the standby mode. Power consumption is greatly re- duced in both modes. Am41PDS3228D May 13, 2002 ...

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... Figure 25. Temporary Sector/Sector Block Unprotect Timing Diagram.............................................................................. 46 Figure 26. Sector/Sector Block Protect and Unprotect Timing Diagram.............................................................................. 47 Alternate CE#f Controlled Erase and Program Operations .... 48 Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Op- eration Timings............................................................................... 49 SRAM AC Characteristics . . . . . . . . . . . . . . . . . . 50 Read Cycle ............................................................................. 50 Figure 28. SRAM Read Cycle—Address Controlled...................... 50 Figure 29. SRAM Read Cycle ........................................................ 51 Am41PDS3228D vs. Frequency ............................................ 35 3 ...

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... SRAM Data Retention . . . . . . . . . . . . . . . . . . . . . 56 Figure 33. CE1#s Controlled Data Retention Mode....................... 56 Figure 34. CE2s Controlled Data Retention Mode......................... 56 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 57 FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm ............. 57 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 58 Revision A (February 21, 2002) .............................................. 58 Revision A+1 (May 13, 2002) ................................................. 58 Am41PDS3228D May 13, 2002 ...

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... May 13, 2002 Am41PDS3228D Flash Memory CC 10 100 100 RY/BY Bit Flash Memory DQ15 to DQ0 V s CCQ SS SSQ 8 M Bit DQ15 to DQ0 Static RAM Am41PDS3228D SRAM 11 10, 11 110 70 110 N/A DQ15 to DQ0 5 ...

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... A20–A0 RY/BY# A20–A0 RESET# STATE CONTROL WE# & CE# COMMAND REGISTER DQ15–DQ0 A20– Upper Bank Address Upper Bank X-Decoder Status Control X-Decoder Lower Bank Lower Bank Address Am41PDS3228D OE# DQ15–DQ0 OE# May 13, 2002 ...

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... DQ11 CIOs DQ5 DQ14 SSOP). The package and/or data integrity may be compromised if the package body is exposed to tem- peratures above 150 C for prolonged periods of time. Am41PDS3228D Flash only A10 NC SRAM only B10 NC Shared F10 NC G10 NC L10 NC M10 NC 7 ...

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... SRAM Power Supply Device Ground (Common Pin Not Connected Internally LOGIC SYMBOL 19 A18–A0 A20–A19 SA CE#f CE1#s CE2s OE# WE# WP#/ACC RESET# UB#s LB#s CIOs Am41PDS3228D DQ15–DQ0 RY/BY# May 13, 2002 ...

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... Am29PDS322D 32 Megabit ( 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation, Page Mode Flash Memory and 8 Mbit ( 8-Bit/512 K x 16-Bit) Static RAM Valid Combinations Order Number Am41PDS3228DT10I Am41PDS3228DB10I T, S Am41PDS3228DT11I Am41PDS3228DB11I May 13, 2002 TAPE AND REEL inches ...

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... Don’t Care SRAM Address Input, Byte Mode Data In Data Out IN OUT at the same time. IH the boot sectors protection will be removed the two outermost boot sector protection depends IH Am41PDS3228D CC WP#/ACC DQ7– DQ15– RESET# (Note 4) DQ0 DQ8 ...

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... Data In Data Out, DNU = Do Not Use IN OUT at the same time. IH the boot sectors protection will be removed the two outermost boot sector protection depends on IH Am41PDS3228D SS WP#/ACC DQ7– DQ15– RESET# (Note 4) DQ0 DQ8 OUT ...

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... WP#/ACC pin. This function is prima- rily intended to allow faster manufacturing throughput at the factory the system asserts V ACC matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, Am41PDS3228D . When CE# is PACC Here again, CE# selects ACC CE Table 3. Page Word Mode ...

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... RESET# pin returns to V Refer to the AC Characteristics tables for RESET# pa- rameters and to Figure 17 for the timing diagram. Output Disable Mode When the OE# input disabled. The output pins are placed in the high impedance state. Am41PDS3228D + ACC ± 0 the RP ± 0.3 V, the de ...

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... Am41PDS3228D (x16) Address Range 000000h–07FFFh 008000h–0FFFFh 010000h–17FFFh 018000h–01FFFFh 020000h–027FFFh 028000h–02FFFFh 030000h–037FFFh 038000h–03FFFFh 040000h–047FFFh 048000h–04FFFFh 050000h–057FFFh 058000h–05FFFFh 060000h–067FFFh 068000h–06FFFFh 070000h–077FFFh 078000h– ...

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... Sector Size (Kwords Am41PDS3228D (x16) Address Range 160000h–167FFFh 168000h–16FFFFh 170000h–177FFFh 178000h–17FFFFh 180000h–187FFFh 188000h–18FFFFh 190000h–197FFFh 198000h–19FFFFh 1A0000h–1A7FFFh 1A8000h–1AFFFFh 1B0000h–1B7FFFh 1B8000h–1BFFFFh 1C0000h–1C7FFFh 1C8000h–1CFFFFh 1D0000h– ...

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... Am41PDS3228D (x16) Address Range 040000h–047FFFh 048000h–04FFFFh 050000h–057FFFh 058000h–05FFFFh 060000h–067FFFh 068000h–06FFFFh 070000h–077FFFh 078000h–07FFFFh 080000h–087FFFh 088000h–08FFFFh 090000h–097FFFh 098000h–09FFFFh 0A0000h–0A7FFFh 0A8000h–0AFFFFh 0B0000h–0B7FFFh 0B8000h– ...

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... SA63 SGA18 SA64 SGA19 SA65 SGA20 SA66 SGA21 SA67 SGA22 SA68 SGA23 SA69 SGA24 SA70 Am41PDS3228D (x16) Address Range 1C0000h–1C7FFFh 1C8000h–1CFFFFh 1D0000h–1D7FFFh 1D8000h–1DFFFFh 1E0000h–1E7FFFh 1E8000h–1EFFFFh 1F0000h–1F7FFFh 1F8000h–1FFFFFh (x16) Address Range 00000h-07FFFh Sector/ A20–A12 ...

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... Once V removed from the RESET# pin, all the previously pro- tected sectors are protected again. Figure 1 shows the algorithm, and Figure 25 shows the timing diagrams, for this feature. Am41PDS3228D on the WP#/ACC pin, the de the WP#/ACC pin, the de – ...

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... Temporary Sector Unprotect Completed (Note 2) Notes: 1. All protected sectors unprotected (If WP#/ACC = V outermost boot sectors will remain protected). 2. All previously protected sectors are protected once again. Figure 1. Temporary Sector Unprotect Operation May 13, 2002 Am41PDS3228D 19 ...

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... Reset PLSCNT = 1 Increment PLSCNT No Yes PLSCNT = 1000? Yes Device failed Sector Unprotect Algorithm Am41PDS3228D START PLSCNT = 1 RESET Wait First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes No All sectors protected? Yes ...

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... V CC cept any write cycles. This protects data during V power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subse- quent writes are ignored until V Am41PDS3228D This IH ID power-up CC ...

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... The autoselect command sequence may be written erase-suspend-read mode. The autoselect command may not be written while the device is actively pro- gramming or erasing. Am41PDS3228D and OE during power up ...

Page 24

... The first cycle must contain the data 90h. The second cycle must contain the data 00h. The device then returns to reading array data. See Figure 3 for the unlock bypass algorithm. Am41PDS3228D 23 ...

Page 25

... The system is not required to provide any con- trols or timings during these operations. Table 10 shows the address and data requirements for the chip erase command sequence. Am41PDS3228D START Write Program Command Sequence Data Poll ...

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... Reading at any address within erase-suspended sec- tors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together ive Am41PDS3228D 25 ...

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... Data Poll to Erasing Bank from System No Data = FFh? Erasure Completed Notes: 1. See Table 10 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer. Figure 5. Erase Operation Am41PDS3228D START Embedded Erase algorithm in progress Yes May 13, 2002 ...

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... The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase 15. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. Am41PDS3228D Fourth Fifth Sixth Addr ...

Page 29

... During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Figure 6. Data# Polling Algorithm Am41PDS3228D Yes No Yes Yes No ...

Page 30

... Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information. Figure 7. Toggle Bit Algorithm Am41PDS3228D /2. The time taken CC ...

Page 31

... DQ3 prior to and following each subsequent sector erase com- mand. If DQ3 is high on the second status check, the last command might not have been accepted. Table 11 shows the status of DQ3 relative to the other status bits. Am41PDS3228D May 13, 2002 ...

Page 32

... DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. May 13, 2002 Table 11. Write Operation Status DQ7 DQ5 (Note 2) DQ6 (Note 1) DQ7# Toggle 0 Toggle 1 No toggle Data Data Data DQ7# Toggle Am41PDS3228D DQ2 DQ3 (Note 2) RY/BY# 0 N/A No toggle Toggle 0 0 N/A Toggle 1 Data Data 1 ...

Page 33

... Operating ranges define those limits between which the func- tionality of the device is guaranteed –2 +2 +0.5 V 2.0 V Figure 9. Maximum Positive Am41PDS3228D ) . . . . . . . . .–40°C to +85° Overshoot Waveform May 13, 2002 ...

Page 34

... WP#/ACC = V CC CCMax ACCMax I = 4.0 mA min I = –2.0 mA –100 µ min . max ACC Am41PDS3228D Min Typ Max 1 MHz 2 0 0.3 V, 0 ...

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... 0 –0 CE1#s V – 0.2 V, CE2 V CC 0.2 V (CE1#s controlled) or CE2 0.2 V (CE2s controlled), CIOs = Other input = 2 Not 100% tested. A Am41PDS3228D Min Typ Max –1.0 1.0 –1.0 1 0.2 1.4 – May 13, 2002 Unit µA µ ...

Page 36

... Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 Note May 13, 2002 1500 2000 2500 Time Frequency in MHz Figure 11. Typical I vs. Frequency CC1 Am41PDS3228D 3000 3500 4000 2 ...

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... Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels INPUTS Steady Changing from Changing from Does Not Apply Center Line is High Impedance State (High Z) Measurement Level Am41PDS3228D 100, 110 ns Unit 1 TTL gate 2 ...

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... AC CHARACTERISTICS SRAM CE#s Timing Parameter JEDEC Std Description — t CE#s Recover Time CCR CE#f CE1#s CE2s Figure 14. Timing Diagram for Alternating May 13, 2002 Test Setup — t CCR t CCR Between SRAM to Flash Am41PDS3228D All Speeds Unit Min CCR t CCR 37 ...

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... Read Toggle and Data# Polling termination on the data pin with a bias Characteristics Addresses Stable t ACC OEH t CE HIGH Z Am41PDS3228D Speed Option 10 11 Min 100 110 Max 100 110 IL Min 40 45 Max Max 100 110 IL Max ...

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... High-Z Output May 13, 2002 Same page Addresses PRC PRC PRC t ACC OEH t t PACC PACC Figure 16. Page Mode Read Timings Am41PDS3228D PACC ...

Page 41

... Description Max Max Min Min Min Min Ready Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms t Ready t RP Figure 17. Reset Timings Am41PDS3228D All Speeds Unit 20 µs 500 ns 500 ns 200 ns 20 µ May 13, 2002 ...

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... Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information. May 13, 2002 CE#f Low During Toggle Bit Read Toggle and Data# Polling Am41PDS3228D Speed Options Unit 10 11 Min 100 110 ns Min ...

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... WPH A0h t BUSY is the true data at the program address. OUT Figure 18. Program Operation Timings Am41PDS3228D Read Status Data (last two cycles WHWH1 Status D OUT VHH May 13, 2002 ...

Page 44

... SA = sector address (for Sector Erase Valid Address for reading status data (see “Flash Write Operation Status”). Figure 20. Chip/Sector Erase Operation Timings May 13, 2002 SADD 555h for chip erase WPH t DH 30h 10 for Chip Erase t BUSY Am41PDS3228D Read Status Data WHWH2 In Complete Progress ...

Page 45

... OEH GHWL Valid Out t SR/W Read Cycle Complement Complement Status Data Status Data Am41PDS3228D Valid PA Valid PA t CPH t CP Valid Valid In In CE#f Controlled Write Cycles VA High Z True Valid Data High Z True Valid Data May 13, 2002 ...

Page 46

... AHT AS t AHT t ASO t CEPH t OEPH t OE Valid Valid Status Status (first read) (second read) Enter Erase Suspend Program Erase Erase Suspend Suspend Read Program Figure 24. DQ2 vs. DQ6 Am41PDS3228D Valid Valid Data Status (stops toggling) Erase Resume Erase Erase Complete Read 45 ...

Page 47

... VIDR CE#f WE# RY/BY# Figure 25. Temporary Sector/Sector Block Unprotect Min Min Min Min Program or Erase Command Sequence t RSP Timing Diagram Am41PDS3228D All Speed Options Unit 500 ns 500 VIDR ...

Page 48

... For sector protect For sector unprotect Figure 26. Sector/Sector Block Protect and Unprotect May 13, 2002 Valid* Valid* Verify 60h 40h Sector/Sector Block Protect: 150 µs, Sector/Sector Block Unprotect Timing Diagram Am41PDS3228D Valid* Status 47 ...

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... See the “Flash Erase And Programming Performance” section for more information Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Am41PDS3228D Speed Options Unit 10 11 100 110 ...

Page 50

... SADD for sector erase 555 for chip erase Data# Polling GHEL t t WHWH1 CPH t BUSY for program PD for program 55 for erase 30 for sector erase 10 for chip erase is the data written to the device. OUT Am41PDS3228D PA DQ7# D OUT 49 ...

Page 51

... Address Data Out Previous Data Valid Note: CE1 CE2s = WE Figure 28. SRAM Read Cycle—Address Controlled UB#s and/or LB Am41PDS3228D 10, 11 Unit Min 70 ns Max 70 ns Max 70 ns Max 35 ns Max 70 ns ...

Page 52

... May 13, 2002 CO1 t CO2 OLZ t BLZ t LZ Data Valid Figure 29. SRAM Read Cycle (Max.) is less than t (Min.) both for a given device and from device to device HZ LZ Am41PDS3228D BHZ t OHZ 51 ...

Page 53

... Note (See Note 4) High-Z t WHZ Data Undefined applied in case a write ends as CE1#s or WE# going high low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when Am41PDS3228D 10, 11 Unit Min 70 ns Min 60 ns Min 0 ns ...

Page 54

... (See Note 5) High-Z applied in case a write ends as CE1#s or WE# going high low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when Am41PDS3228D t (See Note Data Valid High-Z is measured from the beginning of write ...

Page 55

... AS t (See Note 4) WP (See Note 5) High-Z applied in case a write ends as CE1#s or WE# going high low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when Am41PDS3228D t (See Note Data Valid High-Z is measured from the beginning of write ...

Page 56

... V, one pin at a time. CC Test Setup OUT Test Conditions Am41PDS3228D Unit Comments sec Excludes 00h programming prior to erasure (Note 4) sec Excludes system level µs overhead (Note 5) µs , 1,000,000 cycles. Additionally, CC Min Max –1.0 V 12.5 V –1 ...

Page 57

... V – 0.2 V (Note 3.0 V, CE1#s V – 0 (Note 1) See data retention waveforms 0.2 V (CE2s controlled), CIOs = V Data Retention Mode t SDR CE1 0 Data Retention Mode t SDR CE2s < 0.2 V Am41PDS3228D Min Typ Max Unit 1.0 2.2 V 0.5 6 µA (Note RDR ...

Page 58

... PHYSICAL DIMENSIONS FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm May 13, 2002 Am41PDS3228D 57 ...

Page 59

... ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies Figure 30, SRAM Write Cycle—WE# Control Corrected t in Data Out waveform Am41PDS3228D . WHZ May 13, 2002 ...

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