am42dl1612d Meet Spansion Inc., am42dl1612d Datasheet
am42dl1612d
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am42dl1612d Summary of contents
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Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these ...
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Am42DL16x2D Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29DL16xD 16 Megabit ( 8-Bit 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 2 Mbit (128 K x 16-Bit) Static RAM DISTINCTIVE CHARACTERISTICS MCP Features Power ...
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GENERAL DESCRIPTION Am29DL16xD Features The Am29DL16xD family megabit, 3.0 volt-only flash memory device, organized as 1,048,576 words of 16 bits or 2,097,152 bytes of 8 bits each. Word mode data appears on DQ15–DQ0; byte mode data ap- ...
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TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 MCP Block Diagram . . . . . . . . . ...
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Figure 26. Sector/Sector Block Protect and Unprotect Timing Diagram............................................................................... 48 Alternate CE#f Controlled Erase and Program Operations .... 49 Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Op- eration Timings................................................................................ 50 SRAM Read Cycle .................................................................. 51 Figure 28. SRAM Read ...
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PRODUCT SELECTOR GUIDE Part Number Standard Voltage Range: Speed Options V = 2.7–3 Max Access Time (ns) CE# Access (ns) OE# Access (ns) MCP BLOCK DIAGRAM A19 A19 A–1 WP#/ACC RESET# CE#f CIOf A0 ...
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FLASH MEMORY BLOCK DIAGRAM Mux A0–A20 RY/BY# A0–A20 STATE RESET# CONTROL WE# & CE# COMMAND REGISTER BYTE# WP#/ACC DQ0–DQ15 A0–A20 Mux 6 Upper Bank Address Upper Bank X-Decoder Status Control X-Decoder Lower Bank Lower Bank Address ...
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CONNECTION DIAGRAM LB UB A18 A17 DQ1 SS G2 ...
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PIN DESCRIPTION A0–A16 = 17 Address Inputs (Common) A–1, A19–A17 = 4 Address Inputs (Flash) DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE#f = Chip Enable (Flash) CE#s = Chip Enable (SRAM) OE# = Output Enable (Common) WE# = Write Enable ...
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... Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29DL16xD 16 Megabit ( 8-Bit 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 2 Mbit (128 K x 16-Bit) Static RAM Valid Combinations Order Number Am42DL1612DT70I Am42DL1612DB70I Am42DL1612DT85I Am42DL1612DB85I Am42DL1622DT70I Am42DL1622DB70I Am42DL1622DT85I Am42DL1622DB85I T, S Am42DL1632DT70I Am42DL1632DB70I ...
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DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The r egis ter is ...
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Table 1. Device Bus Operations—Flash Word Mode (CIOf = V Operation CE#f CE1#s CE2s OE# WE# (Notes Read from Flash Write to Flash ± Standby 0 Output ...
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Table 2. Device Bus Operations—Flash Byte Mode (CIOf = V Operation CE#f CE1#s CE2s OE# WE# (Notes Read from Flash Write to Flash ± ...
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Word/Byte Configuration The CIOf pin controls whether the device data I/O pins operate in the byte or word configuration. If the CIOf pin is set at logic ‘1’, the device is in word configura- tion, DQ0–DQ15 are active and controlled ...
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Standby Mode When the system is not reading or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance ...
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Table 4. Sector Addresses for Top Boot Sector Devices Sector Address Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 ...
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Table 6. Sector Addresses for Bottom Boot Sector Devices Sector Address Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 ...
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Autoselect Mode The autoselect mode provides manufacturer and de- vice identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended to automatically match a device to be programmed with its corresponding pro- gramming algorithm. ...
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The device is shipped with all sectors unprotected possible to determine whether a sector is pro- tected or unprotected. See the Autoselect Mode section for details. Write Protect (WP#) The Write Protect function provides a hardware method of ...
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START PLSCNT = 1 RESET Wait 1 µs No First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes Set up sector address Sector Protect: Write 60h to sector address with ...
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SecSi (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 64 Kbytes in length, and uses a ...
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Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE#f or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE CE#f = ...
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Addresses Data (Word Mode) 1Bh 0027h 1Ch 0036h 1Dh 0000h 1Eh 0000h 1Fh 0004h 20h 0000h 21h 000Ah 22h 0000h 23h 0005h 24h 0000h 25h 0004h 26h 0000h Addresses Data (Word Mode) 27h 0016h 28h 0002h 29h 0000h 2Ah 0000h ...
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Table 13. Primary Vendor-Specific Extended Query Addresses Data (Word Mode) 40h 0050h 41h 0052h 42h 0049h 43h 0031h 44h 0033h 45h 0001h 46h 0002h 47h 0001h 48h 0001h 49h 0004h 00XXh 4Ah (See Note) 4Bh 0000h 4Ch 0000h 4Dh 0085h ...
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COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device operations. Table 14 defines the valid register com- mand sequences. Writing incorrect address and data values or writing them in the improper se- ...
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Enter SecSi Sector/Exit SecSi Sector Command Sequence The system can access the SecSi Sector region by is- suing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle ...
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Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No Increment Address Last Address? Programming Completed Note: See Table 14 for program command sequence. Figure 3. Program Operation Chip Erase Command Sequence Chip erase ...
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Write Operation Status section for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other com- mands are ignored. However, note that a hardware reset immediately terminates ...
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Command Sequence (Note 1) Addr Read (Note 6) 1 Reset (Note 7) 1 XXX Manufacturer ID Word 4 555 Device ID Word 4 555 SecSi Sector Factory Word 4 555 Protect (Note 9) Sector Protect Verify Word 4 555 (Note ...
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WRITE OPERATION STATUS The device provides several bits to determine the sta- tus of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 16 and the following subsec- tions describe the function of these bits. DQ7 and ...
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RY/BY#: Ready/Busy# The RY/BY dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since ...
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DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit ...
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Status Embedded Program Algorithm Standard Mode Embedded Erase Algorithm Erase Suspended Sector Erase-Suspend- Erase Read Suspend Non-Erase Mode Suspended Sector Erase-Suspend-Program Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –55°C to +125°C Ambient Temperature with Power Applied ...
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DC CHARACTERISTICS CMOS Compatible Parameter Parameter Description Symbol I Input Load Current LI I RESET# Input Load Current LIT I Output Leakage Current LO I ACC Input Leakage Current LIA Flash V Active Read Current CC1 (Notes ...
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DC CHARACTERISTICS (Continued) CMOS Compatible Parameter Parameter Description Symbol Flash Low V Lock-Out Voltage CC V LKO (Note 5) Notes: 1. The I current listed is typically less than 2 mA/MHz, with OE Maximum I specifications ...
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DC CHARACTERISTICS Zero-Power Flash 500 1000 Note: Addresses are switching at 1 MHz Figure 9. I Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 ...
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TEST CONDITIONS Device Under Test C 6.2 kΩ L Note: Diodes are IN3064 or equivalent Figure 11. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM Don’t Care, Any Change Permitted 3.0 V 1.5 V Input 0.0 V Figure 12. Input Waveforms ...
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AC CHARACTERISTICS SRAM CE#s Timing Parameter JEDEC Std Description — t CE#s Recover Time CCR CE#f CE1#s CE2s Figure 13. Timing Diagram for Alternating Between 38 Test Setup — Min t CCR t CCR SRAM to Flash Am42DL16x2D All Speed ...
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AC CHARACTERISTICS Flash Read-Only Operations Parameter JEDEC Std Description t t Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV Output Enable to ...
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AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std RESET# Pin Low (During Embedded Algorithms Ready Read Mode (See Note) RESET# Pin Low (NOT During Embedded Algorithms Ready Read Mode (See Note) t RESET# Pulse Width RP ...
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AC CHARACTERISTICS Flash Word/Byte Configuration (CIOf) Parameter JEDEC Std Description t t CE#f to CIOf Switching Low or High ELFL/ ELFH t CIOf Switching Low to Output HIGH Z FLQZ t CIOf Switching High to Output Active FHQV CE#f OE# ...
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AC CHARACTERISTICS Flash Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time (WE# to Address) AVWL AS Address Setup Time to OE ASO polling t ...
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AC CHARACTERISTICS Program Command Sequence (last two cycles Addresses 555h CE#f t GHWL OE Data RY/BY VCS Notes program address program data Illustration ...
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AC CHARACTERISTICS Erase Command Sequence (last two cycles Addresses 2AAh CE#f t GHWL OE WE Data 55h RY/BY# t VCS Notes sector address (for Sector Erase), ...
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AC CHARACTERISTICS t WC Valid PA Addresses t AH CE#f OE WE# t WPH Valid Data In WE# Controlled Write Cycle Figure 21. Back-to-back Read/Write Cycle Timings t RC Addresses VA t ACC t CE ...
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AC CHARACTERISTICS Addresses CE#f t OEH WE# OE Valid Data DQ6/DQ2 (first read) RY/BY# Note Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array ...
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AC CHARACTERISTICS Temporary Sector/Sector Block Unprotect Parameter JEDEC Std Description t V Rise and Fall Time (See Note) VIDR Rise and Fall Time (See Note) VHH HH RESET# Setup Time for Temporary t RSP Sector/Sector Block Unprotect ...
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AC CHARACTERISTICS RESET# SADD, A6, A1, A0 Sector/Sector Block Protect or Unprotect Data 60h 1 µs CE#f WE# OE# * For sector protect For sector unprotect, A6 ...
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AC CHARACTERISTICS Alternate CE#f Controlled Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time (WE# to Address) AVWL AS Address Setup Time to CE#f Low During Toggle ...
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AC CHARACTERISTICS 555 for program 2AA for erase Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of a program or erase operation ...
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AC CHARACTERISTICS SRAM Read Cycle Parameter Description Symbol t Read Cycle Time RC t Address Access Time Chip Enable to Output CO1 CO2 t Output Enable Access Time OE t LB#s, UB#s to Valid Output BA ...
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AC CHARACTERISTICS Address CE#1s CE2s OE# Data Out High-Z Notes CIOs is low, ignore UB#s/LB#s timing and t are defined as the time at which the outputs achieve the open circuit ...
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AC CHARACTERISTICS SRAM Write Cycle Parameter Description Symbol t Write Cycle Time WC t Chip Enable to End of Write Cw t Address Setup Time AS t Address Valid to End of Write AW t UB#s, LB#s to End of ...
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AC CHARACTERISTICS Address CE1#s CE2s UB#s, LB#s WE# Data In Data Out Notes: 1. CE1#s controlled, if CIOs is low, ignore UB#s and LB#s timing measured from CE1#s going low to the end of write ...
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AC CHARACTERISTICS Address CE1#s CE2s UB#s, LB#s WE# Data In Data Out Notes: 1. UB#s and LB#s controlled, CIOs must be high measured from CE1#s going low to the end of write measured ...
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FLASH ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Byte Program Time Word Program Time Accelerated Byte/Word Program Time Byte Mode Chip Program Time Word Mode (Note 3) Notes: 1. Typical program and erase times assume the ...
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SRAM DATA RETENTION CHARACTERISTICS Parameter Parameter Description Symbol V V for Data Retention Data Retention Current DH t Data Retention Set-Up Time SDR t Recovery Time RDR Note: CE1#s ≥ V – 0.2 V, CE2s ≥ V ...
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PHYSICAL DIMENSIONS FLA069—69-Ball Fine-Pitch Grid Array 0.15 C (2x) 8.00 BSC B 0.97 1.40 (max) 1.07 0.20 (min) 0.40 7.20 BSC 0.80 58 11.00 BSC Pin A1 DATUM A Corner Index Mark 7.20 BSC 0.80 0.40 ...
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REVISION SUMMARY Revision A (October 24, 2001) Initial release. Revision A+1 (March 4, 2002) Ordering Information Changed package marking for Am42DL1642D (4 part numbers). Figure 30, SRAM Write Cycle—WE# Control In Data Out waveform, corrected t BW Revision A+2 (February ...
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Trademarks Copyright © 2002 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this ...
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February 6, 2004 Am42DL16x2D 61 ...
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Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 MCP Block Diagram . . . . . . . . . . . . ...
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Alternate CE#f Controlled Erase and Program Operations .... 49 Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Op- eration Timings................................................................................ 50 SRAM Read Cycle .................................................................. 51 Figure 28. SRAM Read Cycle—Address Controlled....................... 51 Figure 29. SRAM Read Cycle......................................................... 52 SRAM ...
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Am42DL16x2D Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29DL16xD 16 Megabit ( 8-Bit 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 2 Mbit (128 K x 16-Bit) Static RAM DISTINCTIVE CHARACTERISTICS MCP Features Power ...
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GENERAL DESCRIPTION Am29DL16xD Features The Am29DL16xD family megabit, 3.0 volt-only flash memory device, organized as 1,048,576 words of 16 bits or 2,097,152 bytes of 8 bits each. Word mode data appears on DQ15–DQ0; byte mode data ap- ...
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TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 MCP Block Diagram . . . . . . . . . ...
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Figure 26. Sector/Sector Block Protect and Unprotect Timing Diagram............................................................................... 48 Alternate CE#f Controlled Erase and Program Operations .... 49 Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Op- eration Timings................................................................................ 50 SRAM Read Cycle .................................................................. 51 Figure 28. SRAM Read ...
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PRODUCT SELECTOR GUIDE Part Number Standard Voltage Range: Speed Options V = 2.7–3 Max Access Time (ns) CE# Access (ns) OE# Access (ns) MCP BLOCK DIAGRAM A19 A19 A–1 WP#/ACC RESET# CE#f CIOf A0 ...
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FLASH MEMORY BLOCK DIAGRAM Mux A0–A20 RY/BY# A0–A20 STATE RESET# CONTROL WE# & CE# COMMAND REGISTER BYTE# WP#/ACC DQ0–DQ15 A0–A20 Mux 6 Upper Bank Address Upper Bank X-Decoder Status Control X-Decoder Lower Bank Lower Bank Address ...
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CONNECTION DIAGRAM LB UB A18 A17 DQ1 SS G2 ...
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PIN DESCRIPTION A0–A16 = 17 Address Inputs (Common) A–1, A19–A17 = 4 Address Inputs (Flash) DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE#f = Chip Enable (Flash) CE#s = Chip Enable (SRAM) OE# = Output Enable (Common) WE# = Write Enable ...
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... Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29DL16xD 16 Megabit ( 8-Bit 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 2 Mbit (128 K x 16-Bit) Static RAM Valid Combinations Order Number Am42DL1612DT70I Am42DL1612DB70I Am42DL1612DT85I Am42DL1612DB85I Am42DL1622DT70I Am42DL1622DB70I Am42DL1622DT85I Am42DL1622DB85I T, S Am42DL1632DT70I Am42DL1632DB70I ...
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DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The r egis ter is ...
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Table 1. Device Bus Operations—Flash Word Mode (CIOf = V Operation CE#f CE1#s CE2s OE# WE# (Notes Read from Flash Write to Flash ± Standby 0 Output ...
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Table 2. Device Bus Operations—Flash Byte Mode (CIOf = V Operation CE#f CE1#s CE2s OE# WE# (Notes Read from Flash Write to Flash ± ...
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Word/Byte Configuration The CIOf pin controls whether the device data I/O pins operate in the byte or word configuration. If the CIOf pin is set at logic ‘1’, the device is in word configura- tion, DQ0–DQ15 are active and controlled ...
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Standby Mode When the system is not reading or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance ...
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Table 4. Sector Addresses for Top Boot Sector Devices Sector Address Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 ...
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Table 6. Sector Addresses for Bottom Boot Sector Devices Sector Address Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 ...
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Autoselect Mode The autoselect mode provides manufacturer and de- vice identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended to automatically match a device to be programmed with its corresponding pro- gramming algorithm. ...
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The device is shipped with all sectors unprotected possible to determine whether a sector is pro- tected or unprotected. See the Autoselect Mode section for details. Write Protect (WP#) The Write Protect function provides a hardware method of ...
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START PLSCNT = 1 RESET Wait 1 µs No First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes Set up sector address Sector Protect: Write 60h to sector address with ...
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SecSi (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 64 Kbytes in length, and uses a ...
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Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE#f or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE CE#f = ...
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Addresses Data (Word Mode) 1Bh 0027h 1Ch 0036h 1Dh 0000h 1Eh 0000h 1Fh 0004h 20h 0000h 21h 000Ah 22h 0000h 23h 0005h 24h 0000h 25h 0004h 26h 0000h Addresses Data (Word Mode) 27h 0016h 28h 0002h 29h 0000h 2Ah 0000h ...
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Table 13. Primary Vendor-Specific Extended Query Addresses Data (Word Mode) 40h 0050h 41h 0052h 42h 0049h 43h 0031h 44h 0033h 45h 0001h 46h 0002h 47h 0001h 48h 0001h 49h 0004h 00XXh 4Ah (See Note) 4Bh 0000h 4Ch 0000h 4Dh 0085h ...
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COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device operations. Table 14 defines the valid register com- mand sequences. Writing incorrect address and data values or writing them in the improper se- ...
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Enter SecSi Sector/Exit SecSi Sector Command Sequence The system can access the SecSi Sector region by is- suing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle ...
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Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No Increment Address Last Address? Programming Completed Note: See Table 14 for program command sequence. Figure 3. Program Operation Chip Erase Command Sequence Chip erase ...
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Write Operation Status section for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other com- mands are ignored. However, note that a hardware reset immediately terminates ...
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Command Sequence (Note 1) Addr Read (Note 6) 1 Reset (Note 7) 1 XXX Manufacturer ID Word 4 555 Device ID Word 4 555 SecSi Sector Factory Word 4 555 Protect (Note 9) Sector Protect Verify Word 4 555 (Note ...
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WRITE OPERATION STATUS The device provides several bits to determine the sta- tus of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 16 and the following subsec- tions describe the function of these bits. DQ7 and ...
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RY/BY#: Ready/Busy# The RY/BY dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since ...
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DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit ...
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Status Embedded Program Algorithm Standard Mode Embedded Erase Algorithm Erase Suspended Sector Erase-Suspend- Erase Read Suspend Non-Erase Mode Suspended Sector Erase-Suspend-Program Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –55°C to +125°C Ambient Temperature with Power Applied ...
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DC CHARACTERISTICS CMOS Compatible Parameter Parameter Description Symbol I Input Load Current LI I RESET# Input Load Current LIT I Output Leakage Current LO I ACC Input Leakage Current LIA Flash V Active Read Current CC1 (Notes ...
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DC CHARACTERISTICS (Continued) CMOS Compatible Parameter Parameter Description Symbol Flash Low V Lock-Out Voltage CC V LKO (Note 5) Notes: 1. The I current listed is typically less than 2 mA/MHz, with OE Maximum I specifications ...
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DC CHARACTERISTICS Zero-Power Flash 500 1000 Note: Addresses are switching at 1 MHz Figure 9. I Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 ...
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TEST CONDITIONS Device Under Test C 6.2 kΩ L Note: Diodes are IN3064 or equivalent Figure 11. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM Don’t Care, Any Change Permitted 3.0 V 1.5 V Input 0.0 V Figure 12. Input Waveforms ...
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AC CHARACTERISTICS SRAM CE#s Timing Parameter JEDEC Std Description — t CE#s Recover Time CCR CE#f CE1#s CE2s Figure 13. Timing Diagram for Alternating Between 38 Test Setup — Min t CCR t CCR SRAM to Flash Am42DL16x2D All Speed ...
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AC CHARACTERISTICS Flash Read-Only Operations Parameter JEDEC Std Description t t Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV Output Enable to ...
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AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std RESET# Pin Low (During Embedded Algorithms Ready Read Mode (See Note) RESET# Pin Low (NOT During Embedded Algorithms Ready Read Mode (See Note) t RESET# Pulse Width RP ...
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AC CHARACTERISTICS Flash Word/Byte Configuration (CIOf) Parameter JEDEC Std Description t t CE#f to CIOf Switching Low or High ELFL/ ELFH t CIOf Switching Low to Output HIGH Z FLQZ t CIOf Switching High to Output Active FHQV CE#f OE# ...
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AC CHARACTERISTICS Flash Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time (WE# to Address) AVWL AS Address Setup Time to OE ASO polling t ...
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AC CHARACTERISTICS Program Command Sequence (last two cycles Addresses 555h CE#f t GHWL OE Data RY/BY VCS Notes program address program data Illustration ...
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AC CHARACTERISTICS Erase Command Sequence (last two cycles Addresses 2AAh CE#f t GHWL OE WE Data 55h RY/BY# t VCS Notes sector address (for Sector Erase), ...
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AC CHARACTERISTICS t WC Valid PA Addresses t AH CE#f OE WE# t WPH Valid Data In WE# Controlled Write Cycle Figure 21. Back-to-back Read/Write Cycle Timings t RC Addresses VA t ACC t CE ...
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AC CHARACTERISTICS Addresses CE#f t OEH WE# OE Valid Data DQ6/DQ2 (first read) RY/BY# Note Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array ...
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AC CHARACTERISTICS Temporary Sector/Sector Block Unprotect Parameter JEDEC Std Description t V Rise and Fall Time (See Note) VIDR Rise and Fall Time (See Note) VHH HH RESET# Setup Time for Temporary t RSP Sector/Sector Block Unprotect ...
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AC CHARACTERISTICS RESET# SADD, A6, A1, A0 Sector/Sector Block Protect or Unprotect Data 60h 1 µs CE#f WE# OE# * For sector protect For sector unprotect, A6 ...
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AC CHARACTERISTICS Alternate CE#f Controlled Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time (WE# to Address) AVWL AS Address Setup Time to CE#f Low During Toggle ...
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AC CHARACTERISTICS 555 for program 2AA for erase Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of a program or erase operation ...
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AC CHARACTERISTICS SRAM Read Cycle Parameter Description Symbol t Read Cycle Time RC t Address Access Time Chip Enable to Output CO1 CO2 t Output Enable Access Time OE t LB#s, UB#s to Valid Output BA ...
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AC CHARACTERISTICS Address CE#1s CE2s OE# Data Out High-Z Notes CIOs is low, ignore UB#s/LB#s timing and t are defined as the time at which the outputs achieve the open circuit ...
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AC CHARACTERISTICS SRAM Write Cycle Parameter Description Symbol t Write Cycle Time WC t Chip Enable to End of Write Cw t Address Setup Time AS t Address Valid to End of Write AW t UB#s, LB#s to End of ...
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AC CHARACTERISTICS Address CE1#s CE2s UB#s, LB#s WE# Data In Data Out Notes: 1. CE1#s controlled, if CIOs is low, ignore UB#s and LB#s timing measured from CE1#s going low to the end of write ...
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AC CHARACTERISTICS Address CE1#s CE2s UB#s, LB#s WE# Data In Data Out Notes: 1. UB#s and LB#s controlled, CIOs must be high measured from CE1#s going low to the end of write measured ...
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FLASH ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Byte Program Time Word Program Time Accelerated Byte/Word Program Time Byte Mode Chip Program Time Word Mode (Note 3) Notes: 1. Typical program and erase times assume the ...
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SRAM DATA RETENTION CHARACTERISTICS Parameter Parameter Description Symbol V V for Data Retention Data Retention Current DH t Data Retention Set-Up Time SDR t Recovery Time RDR Note: CE1#s ≥ V – 0.2 V, CE2s ≥ V ...
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PHYSICAL DIMENSIONS FLA069—69-Ball Fine-Pitch Grid Array 0.15 C (2x) 8.00 BSC B 0.97 1.40 (max) 1.07 0.20 (min) 0.40 7.20 BSC 0.80 58 11.00 BSC Pin A1 DATUM A Corner Index Mark 7.20 BSC 0.80 0.40 ...
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REVISION SUMMARY Revision A (October 24, 2001) Initial release. Revision A+1 (March 4, 2002) Ordering Information Changed package marking for Am42DL1642D (4 part numbers). Figure 30, SRAM Write Cycle—WE# Control In Data Out waveform, corrected t BW Revision A+2 (February ...
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Trademarks Copyright © 2002 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this ...
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February 6, 2004 Am42DL16x2D 61 ...
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Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 MCP Block Diagram . . . . . . . . . . . . ...
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Alternate CE#f Controlled Erase and Program Operations .... 49 Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Op- eration Timings................................................................................ 50 SRAM Read Cycle .................................................................. 51 Figure 28. SRAM Read Cycle—Address Controlled....................... 51 Figure 29. SRAM Read Cycle......................................................... 52 SRAM ...