m36l0r8060b1 STMicroelectronics, m36l0r8060b1 Datasheet

no-image

m36l0r8060b1

Manufacturer Part Number
m36l0r8060b1
Description
256 Mbit Multiple Bank, Multi-level, Burst Flash Memory And 64 Mbit Burst Psram, 1.8v Supply, Multi-chip Package
Manufacturer
STMicroelectronics
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
m36l0r8060b1ZAQ
Manufacturer:
ST
0
Part Number:
m36l0r8060b1ZAQF
Manufacturer:
ST
Quantity:
5 577
Part Number:
m36l0r8060b1ZAQF
Manufacturer:
ST
0
FEATURES SUMMARY
FLASH MEMORY
June 2005
and 64 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package
MULTI-CHIP PACKAGE
SUPPLY VOLTAGE
ELECTRONIC SIGNATURE
PACKAGE
SYNCHRONOUS / ASYNCHRONOUS READ
SYNCHRONOUS BURST READ SUSPEND
PROGRAMMING TIME
MEMORY ORGANIZATION
DUAL OPERATIONS
SECURITY
1 die of 256 Mbit (16Mb x16, Multiple
Bank, Multi-level, Burst) Flash Memory
1 die of 64 Mbit (4Mb x16) Pseudo SRAM
V
V
Manufacturer Code: 20h
Top Device Code
M36L0R8060T1: 880Dh
Bottom Device Code
M36L0R8060B1: 880Eh
Compliant with Lead-Free Soldering
Processes
Lead-Free Versions
Synchronous Burst Read mode: 54MHz
Asynchronous Page Read mode
Random Access: 85ns
10µs typical Word program time using
Buffer Enhanced Factory Program
command
Multiple Bank Memory Array: 16 Mbit
Banks
Parameter Blocks (Top or Bottom
location)
program/erase in one Bank while read in
others
No delay between read and write
operations
64 bit unique device number
2112 bit user programmable OTP Cells
DDF
PPF
256 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory
= 9V for fast program (12V tolerant)
= V
CCP
= V
DDQF
= 1.7 to 1.95V
Figure 1. Package
PSRAM
BLOCK LOCKING
COMMON FLASH INTERFACE (CFI)
100,000 PROGRAM/ERASE CYCLES per
BLOCK
ACCESS TIME: 70ns
ASYNCHRONOUS PAGE READ
LOW POWER FEATURES
SYNCHRONOUS BURST READ/WRITE
All blocks locked at power-up
Any combination of blocks can be locked
with zero latency
WP
Absolute Write Protection with V
Page Size: 16 words
Subsequent read within page: 20ns
Temperature Compensated Refresh
(TCR)
Partial Array Refresh (PAR)
Deep Power-Down (DPD) Mode
F
for Block Lock-Down
M36L0R8060B1
M36L0R8060T1
TFBGA88 (ZAQ)
8 x 10mm
FBGA
PPF
= V
1/18
SS

Related parts for m36l0r8060b1

m36l0r8060b1 Summary of contents

Page 1

... PPF ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Top Device Code M36L0R8060T1: 880Dh – Bottom Device Code M36L0R8060B1: 880Eh PACKAGE – Compliant with Lead-Free Soldering Processes – Lead-Free Versions FLASH MEMORY SYNCHRONOUS / ASYNCHRONOUS READ – ...

Page 2

... M36L0R8060T1, M36L0R8060B1 TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Package PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Flash Memory Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 PSRAM Component Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. TFBGA Connections (Top view through package SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Address Inputs (A0-A23 Data Input/Output (DQ0-DQ15 Latch Enable (L Clock (K) ...

Page 3

... Table 8. PSRAM DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. TFBGA88 8x10mm, 8x10 ball array - 0.8mm pitch, Bottom View Package Outline . . . . 15 Table 9. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Data PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 10. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 REVISION HISTORY Table 11. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 M36L0R8060T1, M36L0R8060B1 3/18 ...

Page 4

... M36L0R8060T1, M36L0R8060B1 SUMMARY DESCRIPTION The M36L0R8060T1 and M36L0R8060B1 com- bine two memory devices in a Multi-Chip Package: a 256-Mbit, Multiple Bank Flash memory, the M30L0R8000T0 or M30L0R8000B0, a 64-Mbit PseudoSRAM, the M69KB096AA. This document should be read in conjunction with the M30L0R8000x0 and datasheets. Recommended operating conditions do not allow more than one memory to be active at the same time ...

Page 5

... F W Write Enable input F RP Reset input F WP Write Protect input F PSRAM Signals E Chip Enable Input P G Output Enable Input P W Write Enable Input P CR Configuration Register Enable Input P UB Upper Byte Enable Input P LB Lower Byte Enable Input P M36L0R8060T1, M36L0R8060B1 5/18 ...

Page 6

... M36L0R8060T1, M36L0R8060B1 Figure 3. TFBGA Connections (Top view through package A18 A17 DQ8 G P DQ0 6/ A19 DDF A23 PPF ...

Page 7

... PSRAM Output Enable ( provides a high speed tri-state control, allow- P ing fast read/write cycles to be achieved with the common I/O data bus. M36L0R8060T1, M36L0R8060B1 , the device is in active mode. IH the Flash memory The Output Enable F ) ...

Page 8

... M36L0R8060T1, M36L0R8060B1 PSRAM Upper Byte Enable (UB Byte En-able gates the data on the Upper P Byte Data Inputs/Outputs (DQ8-DQ15 from the upper part of the selected address during a Write or Read operation. PSRAM Lower Byte Enable (LB Byte Enable gates the data on the Lower P Byte Data Inputs/Outputs (DQ0-DQ7 from the lower part of the selected address during a Write or Read operation ...

Page 9

... 256 Mbit RP F Flash WP Memory DDF DDQF PPF V CCP Mbit G P PSRAM M36L0R8060T1, M36L0R8060B1 WAIT V SS DQ0-DQ15 AI09314b 9/18 ...

Page 10

... M36L0R8060T1, M36L0R8060B1 Table 2. Main Operating Modes Operation Flash Read Flash Write Flash Address Latch Flash Output Disable V Flash Standby Flash Reset PSRAM Read PSRAM Write The Flash memory must be disabled ...

Page 11

... European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. plied. Exposure to Absolute Maximum Rating con- ditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality docu- ments. Parameter PPFH M36L0R8060T1, M36L0R8060B1 Value Min Max –25 85 –25 85 – ...

Page 12

... M36L0R8060T1, M36L0R8060B1 DC AND AC PARAMETERS This section summarizes the operating measure- ment conditions, and the DC and AC characteris- tics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Table 4. Operating and AC Measurement Conditions Parameter ...

Page 13

... I V Supply Current (Read) PP2 PP (1) V Supply Current (Standby PP3 Note: 1. Sampled only, not 100% tested Dual Operation current is the sum of read and program or erase currents. DD M36L0R8060T1, M36L0R8060B1 Test Condition DDQF DDQF OUT ...

Page 14

... M36L0R8060T1, M36L0R8060B1 Table 7. Flash Memory DC Characteristics - Voltages Symbol Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage Program Voltage-Logic PP1 Program Voltage Factory PPH PP V Program or Erase Lockout PPLK V V Lock Voltage ...

Page 15

... SE 0.400 FE1 millimeters Min Max 1.200 0.200 0.300 0.400 7.900 8.100 0.100 9.900 10.100 – – M36L0R8060T1, M36L0R8060B1 e b ddd A2 A1 BGA-Z42 inches Typ Min 0.0079 0.0335 0.0138 0.0118 0.3150 0.3110 0.2205 0.3937 0.3898 0.2835 0.3465 0.0315 – 0.0472 ...

Page 16

... M36L0R8060T1, M36L0R8060B1 PART NUMBERING Table 10. Ordering Information Scheme Example: Device Type M36 = Multi-Chip Package (Multiple Flash + RAM) Flash 1 Architecture L = Multilevel, Multiple Bank, Burst mode Flash 2 Architecture Die Operating Voltage 1.7 to 1.95V DDF CCP DDQF Flash 1 Density 8 = 256 Mbits Flash 2 Density ...

Page 17

... Table 11. Document Revision History Date Version 15-Oct-2004 0.1 First Issue 29-Apr-2004 0.2 Part Number M69KB096A changed to M69KB096AA throughout document. Status changed from Preliminary to Full Datasheet. 24-June-2005 0.3 modified. Signal changed from M36L0R8060T1, M36L0R8060B1 Revision Details Table 6., Table throughout the document. DDQ DDQF and Table 8. ...

Page 18

... M36L0R8060T1, M36L0R8060B1 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...

Related keywords