k4t1g084qa-zce6 Samsung Semiconductor, Inc., k4t1g084qa-zce6 Datasheet
k4t1g084qa-zce6
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... A-die DDR2 SDRAM 1Gb A-die DDR2 SDRAM Specification INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS " ...
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... A-die DDR2 SDRAM Contents 0. Ordering Information 1. Key Feature 2. Package Pinout/Mechanical Dimension & Addressing 2.1 Package Pinout & Mechanical Dimension 2.2 Input/Output Function Description 2.3 Addressing 3. Absolute Maximum Rating 4. AC & DC Operating Conditions & Specifications Page DDR2 SDRAM Rev. 1.1 Aug. 2005 ...
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... A-die DDR2 SDRAM Ordering Information Organization DDR2-667 5-5-5 256Mx4 K4T1G044QA-ZCE6 128Mx8 K4T1G084QA-ZCE6 64Mx16 K4T1G164QA-ZCE6 Note 1 : Speed bin is in order of CL-tRCD-tRP. Note 2 : x4/x8 Package - including 8 dummy balls. Key Features Speed CAS Latency tRCD(min) tRP(min) tRC(min) • JEDEC standard 1.8V ± 0.1V Power Supply • VDDQ = 1.8V ± 0.1V • ...
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... A-die DDR2 SDRAM Package Pinout/Mechanical Dimension & Addressing Package Pinout x4 package pinout (Top View) : 68ball FBGA Package 1 NC VDD NC VDDQ NC VDDL BA2 VSS VDD NC Ball Locations (x4) Top View (See the balls through the Package ...
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... A-die DDR2 SDRAM x8 package pinout (Top View) : 68ball FBGA Package 1 NC VDD DQ6 VDDQ DQ4 VDDL BA2 VSS VDD NC Ball Locations (x8) Top View (See the balls through the Package ...
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... A-die DDR2 SDRAM x16 package pinout (Top View) : 84ball FBGA Package 1 2 VDD NC DQ14 VSSQ VDDQ DQ9 DQ12 VSSQ VDD NC DQ6 VSSQ VDDQ DQ1 DQ4 VSSQ VDDL VREF CKE BA2 BA0 A10/AP VSS A3 A7 VDD A12 Ball Locations (x16) Top View (See the balls through the Package) ...
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... A-die DDR2 SDRAM FBGA Package Dimension(x4/x8) #A1 11.00 ± 0.10 3. INDEX MARK 1.60 0. ...
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... A-die DDR2 SDRAM FBGA Package Dimension(x16) #A1 11.00 ± 0.10 3. INDEX MARK 1.60 0. ...
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... Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on CS Input systems with multiple Ranks considered part of the command code. On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS, RDQS, RDQS, and DM signal for x4/x8 configurations. For ODT Input x16 configuration, ODT is applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM signal ...
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... A-die DDR2 SDRAM 1Gb Addressing Configuration # of Bank Bank Address Auto precharge Row Address Column Address * Reference information: The following tables are address mapping information for other densities. 256Mb Configuration # of Bank Bank Address Auto precharge Row Address Column Address 512Mb Configuration # of Bank ...
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... Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. ...
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... TOPER Operating Temperature Note : 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2 standard operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3 required, and to enter to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate ...
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... A-die DDR2 SDRAM Differential input AC logic Level Symbol Parameter V (AC) AC differential input voltage ID V (AC) AC differential cross point voltage IX Notes : 1. V (AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or ID UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS) ...
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... The absolute value of the slew rate as measured from equal to or greater than the slew rate as measured from AC to AC. This is guaran- teed by design and characterization. 6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process and represents only the DRAM uncertainty. Output slew rate load : 7 ...
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... A-die DDR2 SDRAM IDD Specification Parameters and Test Conditions (IDD values are for full operating range of Voltage and Temperature, Notes Symbol Proposed Conditions Operating one bank active-precharge current CK(IDD RC(IDD), t RAS = t RASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands; ...
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... A-die DDR2 SDRAM Notes : 1. IDD specifications are tested after the device is properly initialized 2. Input slew rate is specified by AC Parametric Test Condition 3. IDD parameters are specified with ODT disabled. 4. Data bus consists of DQ, DM, DQS, DQS\, RDQS, RDQS\, LDQS, LDQS\, UDQS, and UDQS\. IDD values must be met with all combinations of EMRS bits 10 and 11 ...
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... IDD5B 220 IDD6 15 IDD7 350 256Mx4(K4T1G044QA) 533@CL=4 CD5 LD5 120 120 215 280 128Mx8(K4T1G084QA) 533@CL=4 CD5 LD5 130 130 215 280 64Mx16(K4T1G164QA) 533@CL=4 CD5 LD5 110 130 8 15 ...
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... A-die DDR2 SDRAM Input/Output capacitance Parameter Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS Input/output capacitance delta, DQ, DM, DQS, DQS Electrical Characteristics & AC Timing for DDR2-667/533/400 (0 qC < ...
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... A-die DDR2 SDRAM Timing Parameters by Speed Grade (Refer to notes for informations related to this table at the bottom) Parameter Symbol DQ output access time from CK/CK tAC DQS output access time from CK/CK tDQSCK CK high-level width tCH CK low-level width tCL CK half period tHP Clock cycle time, CL=x ...
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... A-die DDR2 SDRAM Parameter Symbol CAS to CAS command delay tCCD Write recovery time tWR Auto precharge write recovery + precharge time tDAL Internal write to read command delay tWTR Internal read to precharge command delay tRTP Exit self refresh to a non-read command tXSNR Exit self refresh to a read command ...
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... The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level for differential sig- nals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal. 3. DDR2 SDRAM output slew rate test load Output slew rate is characterized under the test conditions as shown in the following figure. ...
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... A-die DDR2 SDRAM 4. Differential data strobe DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM dependent. In single ended mode, timing relationships are measured relative to the rising or falling these timing relationships are measured relative to the crosspoint of DQS and its design and characterization ...
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... A-die DDR2 SDRAM Specific Notes for dedicated AC parameters 9. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit timing. ...
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... A-die DDR2 SDRAM 18. tIS and tIH (input setup and hold) derating. 2.0 V/ns 'tIS 4.0 +187 3.5 +179 3.0 +167 2.5 +150 2.0 +125 1.5 +83 1.0 0 0.9 -11 Command/ Address Slew 0.8 -25 rate(V/ns) 0.7 -43 0.6 -67 0.5 -110 0.4 -175 0.3 -285 0.25 -350 0.2 -525 0.15 -800 'tIS and 'tIH Derating Values for DDR2-667, DDR2-800 2.0 V/ns 'tIS 4.0 +150 3.5 +143 3.0 +133 2 ...
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... A-die DDR2 SDRAM 19. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 20. MIN ( tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this greater than the minimum specification limits for tCL and tCH) ...
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... A-die DDR2 SDRAM tHZ tRPST end point T2 T1 tHZ,tRPST end point = 2*T1-T2 29. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the V ential data strobe crosspoint for a rising signal, and from the input signal crossing at the V signal applied to the device under test ...
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... A-die DDR2 SDRAM 31. Input waveform timing is referenced from the input signal crossing at the V device under test. 32. Input waverorm timing is referenced from the input signal crossing at the V device under test 33. tWTR is at lease two clocks (2 * tCK) independent of operation frequency. 34. Input waveform timing with single-ended data strobe enabled MR[bit10 referenced from the input signal crossing at the VIH(ac) level to the single-ended data strobe crossing VIH/L(dc) at the start of its transition for a rising signal, and from the input signal crossing at the VIL(ac) level to the sin- gle-ended data strobe crossing VIH/L(dc) at the start of its transition for a falling signal applied to the device under test ...
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... A-die DDR2 SDRAM Revision History Version 1.0 (Jul. 2005) - Initial Release Version 1.1 (Aug. 2005) - Revised IDD Spec Table Page DDR2 SDRAM Rev. 1.1 Aug. 2005 ...