k4s160822d Samsung Semiconductor, Inc., k4s160822d Datasheet
k4s160822d
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k4s160822d Summary of contents
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... K4S160822D 2Mx8 SDRAM Samsung Electronics reserves the right to change products or specification without notice 8bit x 2 Banks Synchronous DRAM LVTTL Revision 1.0 October 1999 - 1 - CMOS SDRAM Rev. 1.0 (Oct. 1999) ...
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... K4S160822D Revision History Revision 1.0 (October 1999 CMOS SDRAM Rev. 1.0 (Oct. 1999) ...
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... LCBR CLK CKE GENERAL DESCRIPTION The K4S160822D is 16,777,216 bits synchronous high data rate Dynamic RAM organized 1,048,576 words by 8 bits, fabricated with SAMSUNG s high performance CMOS technol- ogy. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle ...
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... K4S160822D PIN CONFIGURATION (Top view) A10/AP PIN FUNCTION DESCRIPTION Pin Name CLK System clock CS Chip select CKE Clock enable /AP Address Bank select address RAS Row address strobe CAS Column address strobe WE Write enable DQM Data input/output mask DQ ~ Data input/output ...
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... K4S160822D ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative Voltage on V supply relative Storage temperature Power dissipation Short circuit current Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. ...
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... Operating current I CC4 (Burst mode) Refresh current I CC5 Self refresh current I CC6 Notes : 1. Unless otherwise notes, Input level is CMOS(V 2. Measured with outputs open. 3. Refresh period is 32ms. 4. K4S160822DT-G** 5. K4S160822DT-F Test Condition Latency Burst length = (min CKE ...
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... K4S160822D AC OPERATING TEST CONDITIONS Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition 3.3V 1200 Output 50pF 870 (Fig output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) ...
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... K4S160822D AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter Symbol CAS latency=3 CLK cycle time t CAS latency=2 CAS latency=3 CLK to valid t output delay CAS latency=2 CAS latency=3 Output data t hold time CAS latency=2 CLK high pulse width t CLK low pulse width Input setup time ...
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... K4S160822D IBIS SPECIFICATION I Characteristics (Pull-up) OH 100MHz 100MHz Voltage Min Max (V) I (mA) I (mA) 3.45 -2.4 3.3 -27.3 3.0 0.0 -74.1 2.6 -21.1 -129.2 2.4 -34.1 -153.3 2.0 -58.7 -197.0 1.8 -67.3 -226.2 1.65 -73.0 -248.0 1.5 -77.9 -269.7 1.4 -80.8 -284.3 1.0 -88.6 -344.5 0.0 -93.0 -502.4 I Characteristics (Pull-down) OL 100MHz 100MHz Voltage Min Max (V) I (mA) I (mA) 0.0 0.0 0.0 0.4 27.5 70.2 0.65 41.8 107.5 0.85 51.6 133.8 1.0 58.0 151.2 1.4 70.7 187.7 1.5 72.9 194.4 1.65 75.4 202.5 1.8 77.0 208.6 1.95 77.6 212.0 3.0 80.3 219.6 3.45 81.4 222.6 66MHz and 100MHz Pull- ...
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... K4S160822D V Clamp @ CLK, CKE, CS, DQM & (V) I (mA) DD 0.0 0.0 0.2 0.0 0.4 0.0 0.6 0.0 0.7 0.0 0.8 0.0 0.9 0.0 1.0 0.23 1.2 1.34 1.4 3.02 1.6 5.06 1.8 7.35 2.0 9.83 2.2 12.48 2.4 15.30 2.6 18.31 V Clamp @ CLK, CKE, CS, DQM & (V) I (mA) SS -2.6 -57.23 -2.4 -45.77 -2.2 -38.26 -2.0 -31.22 -1.8 -24.58 -1.6 -18.37 -1.4 -12.56 -1.2 -7.57 -1.0 -3.37 -0.9 -1.75 -0.8 -0.58 -0.7 -0.05 -0.6 0.0 -0.4 0.0 -0.2 0.0 0.0 0.0 Minimum V clamp characteristic DD (Referenced Voltage I (mA) Minimum V clamp current -10 -20 -30 -40 -50 -60 Voltage I (mA CMOS SDRAM ) Rev ...
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... K4S160822DT-H CAS Frequency Latency 100MHz (10.0ns) 2 83MHz (12.0ns) 2 75MHz (13.0ns) 2 66MHz (15.0ns) 2 60MHz (16.7ns) 2 K4S160822DT-L CAS Frequency Latency 100MHz (10.0ns) 3 83MHz (12.0ns) 2 75MHz (13.0ns) 2 66MHz (15.0ns) 2 60MHz (16.7ns) 2 K4S160822DT-10 CAS Frequency Latency 100MHz (10.0ns) 3 83MHz (12.0ns) 3 75MHz (13 ...
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... K4S160822D SIMPLIFIED TRUTH TABLE COMMAND Register Mode Register Set Auto Refresh Entry Refresh Self Refresh Exit Bank Active & Row Addr. Read & Auto Precharge Disable Column Address Auto Precharge Enable Write & Auto Precharge Disable Column Address Auto Precharge Enable ...
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... K4S160822D MODE REGISTER FIELD TABLE TO PROGRAM MODES Register Programmed with MRS BA A /AP A Address 10 Function RFU RFU W.B.L Test Mode A A Type Mode Register Set 0 1 Reserved 1 0 Reserved 1 1 Reserved Write Burst Length Length Burst 1 Single Bit POWER UP SEQUENCE 1. Apply power and start clock, Attempt to maintain CKE= " ...
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... K4S160822D BURST SEQUENCE (BURST LENGTH = 4) Initial Address BURST SEQUENCE (BURST LENGTH = 8) Initial Address ...
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... K4S160822D DEVICE OPERATIONS CLOCK (CLK) The clock input is used as the reference for all SDRAM opera- tions. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between V and V . During operation with CKE high all inputs are ...
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... K4S160822D DEVICE OPERATIONS (Continued) MODE REGISTER SET (MRS) The mode register stores the data for controlling the various operating modes of SDRAM. It programs the CAS latency, burst type, burst length, test mode and various vendor specific options to make SDRAM useful for variety of different applications. The ...
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... K4S160822D DEVICE OPERATIONS (Continued) DQM OPERATION The DQM is used to mask input and output operations. It works similar to OE during read operation and inhibits writing during write operation. The read latency is two cycles from DQM and zero cycle for write, which means DQM masking occurs two cycles later in read cycle and occurs in the same cycle during write cycle ...
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... K4S160822D BASIC FEATURE AND FUNCTION DESCRIPTIONS 1. CLOCK Suspend 1) Clock Suspended During Write (BL=4) CLK CMD WR CKE Masked by CKE Internal CKE DQ(CL2 DQ(CL3 Not Written 2. DQM Operation 1) Write Mask (BL=4) CLK WR CMD DQM Masked by DQM DQ(CL2 DQ(CL3 ...
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... K4S160822D 3. CAS Interrupt (I) Note 1 1) Read interrupted by Read (BL=4) CLK CMD ADD DQ(CL2 DQ(CL3) tCCD Note 2 2) Write interrupted by Write (BL=2) CLK CMD WR WR tCCD Note ADD tCDL Note 3 *Note : 1. By " Interrupt" meant to stop burst read/write by external command before the end of burst. ...
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... K4S160822D 3. CAS Interrupt (I) Note 1 1) Read interrupted by Read (BL=4) CLK CMD ADD DQ(CL2 DQ(CL3) tCCD Note 2 2) Write interrupted by Write (BL=2) CLK CMD WR WR tCCD Note ADD tCDL Note 3 *Note : 1. By " Interrupt" meant to stop burst read/write by external command before the end of burst. ...
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... K4S160822D ( Continued ) (b) CL=3, BL=4 CLK i) CMD RD DQM DQ ii) CMD RD DQM DQ RD iii) CMD DQM DQ RD iii) CMD DQM DQ RD iv) CMD DQM DQ 5. Write Interrupted by Precharge & DQM CLK WR CMD DQM *Note : 1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out. ...
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... K4S160822D 6. Precharge 1) Normal Write (BL=4) CLK WR CMD Normal Read (BL=4) CLK CMD RD DQ(CL2) DQ(CL3) 7. Auto Precharge 1) Normal Write (BL=4) CLK WR CMD Normal Read (BL=4) CLK CMD RD DQ(CL2) DQ(CL3) *Note : Last data in to row precharge delay RDL 2. Number of valid output data after row precharge : for CAS Latency = respectively. ...
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... K4S160822D 8. Burst Stop & Interrupted by Precharge 1) Normal Write (BL=4) CLK WR CMD DQM Read Interrupted by Precharge (BL=4) CLK CMD RD DQ(CL2) DQ(CL3) 9. MRS 1) Mode Register Set CLK Note 4 CMD PRE tRP *Note : CLK RDL CLK ; Last data in to burst stop delay. ...
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... K4S160822D 10. Clock Suspend Exit & Power Down Exit 1) Clock Suspend (=Active Power Down) Exit CLK CKE Internal Note 1 CLK CMD 11. Auto Refresh & Self Refresh 1) Auto Refresh & Self Refresh Note 3 CLK Note 4 CMD PRE CKE tRP 2) Self Refresh Note 6 CLK ...
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... K4S160822D 12. About Burst Type Control Sequential Counting Basic MODE Interleave Counting Random Random column Access MODE CLK CCD 13. About Burst Length Control 1 2 Basic MODE 4 8 Full Page Special BRSW MODE Random Burst Stop MODE RAS Interrupt (Interrupted by Precharge) Interrupt ...
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... K4S160822D FUNCTION TRUTH TABLE (TABLE 1) Current CS RAS CAS State IDLE Row Active Read ...
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... K4S160822D FUNCTION TRUTH TABLE (TABLE 1) Current CS RAS CAS State Row Activating Refreshing Mode Register Accessing Abbreviations : RA = Row Address NOP = No Operation Command *Note : 1 ...
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... K4S160822D FUNCTION TRUTH TABLE (TABLE 2) CKE CKE Current CS n State (n- Self Refresh All Banks Precharge Power Down All ...
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... Cb Cc tSH *Note 2,3 *Note 2,3 *Note *Note 3 *Note 3 tSH tSAC Qa Db tSLZ tSS tOH tSH tSS tSS tSH Write Read - 29 CMOS SDRAM tRP Rb *Note *Note Row Active Precharge Rev.1.0 (Mar. 1999 Don't care ...
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... Disable auto precharge, leave bank A active at end of burst. Disable auto precharge, leave bank B active at end of burst. Enable auto precharge, precharge bank A at end of burst. Enable auto precharge, precharge bank B at end of burst. Precharge Bank A Bank B Both Banks - 30 CMOS SDRAM Rev.1.0 (Mar. 1999) ...
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... CAS ADDR BA A /AP 10 High DQM High level is necessary Precharge Auto Refresh (All Banks tRC Auto Refresh - 31 CMOS SDRAM tRC Key RAa RAa Mode Register Set Row Active (A-Bank) : Don't care Rev.1.0 (Mar. 1999) 19 ...
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... Read (A-Bank) (A-Bank) *Note : 1. Minimum row cycle times is required to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] number of valid output data is available after Row precharge. Last valid output will be Hi-Z(t 3. Access time from Row active command Ouput will be Hi-Z after the end of burst. ( & ...
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... Cb0 Cc0 Qa0 Qa1 Qb0 Qb1 Qb2 Dc0 Qa0 Qa1 Qb0 Qb1 Dc0 *Note 1 Read Write (A-Bank) (A-Bank) before Row precharge, will be written. RDL - 33 CMOS SDRAM *Note 2 Cd0 tRDL Dc1 Dd0 Dd1 Dc1 Dd0 Dd1 tCDL *Note 3 Write ...
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... HIGH CAc CBb QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 Read Read (B-Bank) (A-Bank CMOS SDRAM *Note 2 CAe CBd QBd0 QBd1 QAe0 QAe1 QBd0 QBd1 QAe0 QAe1 ...
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... To interrupt burst write by Row precharge, both the write and the precharge banks must be the same HIGH RBb CBb RBb DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 DBd1 tCDL Write (B-Bank CMOS SDRAM *Note 2 CAc CBd tRDL *Note 1 Write Precharge (A-Bank) (Both Banks) Write (B-Bank) Rev ...
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... HIGH RBb RBb QAa0 QAa1 QAa2 QAa3 QAa0 QAa1 QAa2 QAa3 Precharge (A-Bank) Row Active (B-Bank CMOS SDRAM CBb RAc CAc RAc *Note 1 tCDL DBb0 DBb1 DBb2 DBb3 QAc0 QAc1 QAc2 DBb0 DBb1 DBb2 DBb3 ...
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... Cb Qa0 Qa1 Qb0 Qb1 Qb2 Qa0 Qa1 Qb0 Qb1 Read without Auto Precharge precharge(B-Bank) (B-Bank) Auto Precharge Start Point (A-Bank)*¨ç CMOS SDRAM Qb3 Qb2 Qb3 Write with Row Active Auto Precharge (A-Bank) (A-Bank) Rev.1.0 (Mar. 1999) ...
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... Qa2 Qa3 Qa0 Qa1 Qa2 Qa3 *¨ç Read with Auto Precharge Read with Start Point Auto Precharge (A-Bank) (A-Bank) (B-Bank) Row Active (B-Bank CMOS SDRAM Qb0 Qb1 Qb2 Qb3 Qb0 Qb1 Qb2 Qb3 Auto Precharge Start Point ...
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... DQM Row Active Read *Note : 1. DQM is needed to prevent bus contention Qa0 Qa1 Qa2 Qa3 tSHZ Clock Read Suspension - 39 CMOS SDRAM Qb0 Qb1 Dc0 Dc2 tSHZ *Note 1 Write Read DQM DQM Write Clock Suspension Rev ...
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... HIGH CAb 1 QAa0 QAa1 QAa2 QAa3 QAa4 *Note 2 2 QAa0 QAa1 QAa2 QAa3 QAa4 Burst Stop Read (A-Bank CMOS SDRAM QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 Precharge (A-Bank) : Don't care Rev ...
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... Input data after Row precharge cycle will be masked internally. 3. Burst stop is valid at every burst length HIGH CAb tBDL DAb0 DAb1 DAb2 DAb3 DAb4 Burst Stop Write (A-Bank) RDL CMOS SDRAM tRDL *Note 2 DAb5 Precharge (A-Bank) : Don't care Rev.1.0 (Mar. 1999) 19 ...
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... HIGH RBb CAb RAc RBb RAc QAb0 QAb1 QAb0 QAb1 Row Active (A-Bank) Read with Auto Precharge (A-Bank) "High" at MRS (Mode Register Set CMOS SDRAM *Note 2 CBc CAd DBc0 QAd0 QAd1 DBc0 QAd0 QAd1 Read Precharge (A-Bank) ...
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... Can not violate minimum refresh specification. (32ms tSS tSS *Note Row Active Active Precharge Active Power-down Power-down Power-down Exit Entry Exit - 43 CMOS SDRAM tSHZ Qa0 Qa1 Qa2 Read Precharge Rev.1.0 (Mar. 1999 Don't care ...
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... Hi-Z Self Refresh Exit is required before exit from self refresh. RAS - 44 CMOS SDRAM tRCmin *Note 6 *Note 7 Auto Refresh : Don't care Rev.1.0 (Mar. 1999) 19 ...
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... CS, RAS, CAS, & WE activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new RAS activation. 3. Please refer to Mode Register Set table. Auto Refresh Cycle Auto Refresh - 45 CMOS SDRAM HIGH ...
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... K4S160822D PACKAGE DIMENSIONS 50-TSOP2-400F #50 #1 21.35 0.841 20.95 0.825 0.10 MAX 0.004 0.30 0.805 ( ) 0.012 0.032 #26 #25 MAX 0.10 0.004 0.047 +0.10 0.80 0.05 -0.05 MIN +0.004 0.0315 0.002 -0.002 - 46 CMOS SDRAM Unit : Millimeters 0~8 0.25 TYP 0.010 +0.075 0.125 -0.035 +0.003 0.005 -0.001 1.20 1.00 0.10 MAX 0.039 0.004 Rev. 1.0 (Oct. 1999) ...