hb288064mm1 Renesas Electronics Corporation., hb288064mm1 Datasheet
hb288064mm1
Related parts for hb288064mm1
hb288064mm1 Summary of contents
Page 1
... It is accessible via a dedicated serial interface optimized for fast and reliable data transmission. This interface allows several cards to be stacked by through connecting their peripheral contacts. The HB288064MM1 is fully compatible to a new consumer standard, called the MultiMediaCard system standard defined in the MultiMediaCard system specification [1]. The MultiMediaCard system is a new mass-storage system based on innovations in semiconductor technology ...
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... HB288064MM1 MultiMediaCard system standard compatibility System specification version 2.11 compliant SPI interface supported Block and partial block read supported (Command classes 0 and 2) Stream read supported (Command class 1) Block write and erase supported (Command classes 4 and 5) Group write protection (Command classes 6) Stream write supported (Command classes 3) ...
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... Generator Flash control All units in the HB288064MM1 are clocked by an internal clock generator. The Interface driver unit synchronizes the DAT and CMD signals from external CLK to the internal used clock signal. The card is controlled by the three line MultiMediaCard interface containing the signals: CMD, CLK, DAT (refer to Chapter “ ...
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... The CMD signal has two operation modes: open drain for initialization mode and push pull for fast command transfer. Commands are sent from the MultiMediaCard bus master to the HB288064MM1 and responses vice versa. DAT bidirectional data channel with a width of one line. The DAT signal of the HB288064MM1 operates in push pull mode MultiMediaCard Host All MultiMediaCards are connected directly to the lines of the MultiMediaCard bus ...
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... CLK SS2 7 DAT I/O/PP Note power supply; I: input; O: output; PP: push-pull; OD: open-drain; NC: No connection or V DAT V SS2 CLK SS1 CMD Interface driver MultiMediaCard Mode I/O-drivers 1 Description No connection Command/Response Ground Power supply Clock Ground Data enable enable HB288064MM1 IH 5 ...
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... HB288064MM1 SPI Mode The Serial Peripheral Interface (SPI general-purpose synchronous serial interface originally found on certain Motorola microcontrollers. The MultiMediaCard SPI interface is compatible with SPI hosts available on the market. As any other SPI device the MultiMediaCard SPI interface consists of the following four signals: CS: Host to card Chip Select signal ...
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... S: power supply; I: input; O: output; PP: push-pull; OD: open-drain; NC: No connection or V SPI Description Name Reserved for future use CS Command/Response DI Ground V SS Power supply V CC Clock SCLK Ground V SS2 Data DO HB288064MM1 Type Description I Chip select (neg true) I Data in S Ground S Power supply I Clock S Ground O/PP Data out IH 7 ...
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... Programmed by the manufacturer. Partially programmable by the user. CID and RCA are used for identifying and addressing the HB288064MM1. The third register contains the card specific data record. This record is a set of information fields to define the operation conditions of the HB288064MM1. For the user the CID and the CSD are read only registers. They are read out by special commands (refer to Chapter “ ...
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... Standby State with the command SELECT_DESELECT_CARD (CMD7). The RCA is programmed with the command SET_RELATIVE_ADDRESS (CMD3) during the initialization procedure. The content of this register is lost after power down. The default value is assigned when an internal reset is applied by the power up detection unit of the HB288064MM1. Width 8 ...
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... HB288064MM1 Card Specific Data (CSD) The card specific data register describes how to access the card content. The CSD defines card operating parameters like maximum data access time, data transfer speed. The CSD Fields Name Field CSD structure CSD_STRUCTURE Spec version SPEC_VERS Reserved — ...
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... The following section describes the CSD fields and their values for the HB288064MM1: CSD_STRUCTURE CSD Register Structure CSD_STRUCTURE ‘01’ The CSD version of the HB288064MM1 is related to the “MultiMediaCard system specification, Version 2.11”. The parameter CSD_STRUCTURE has permanently the value 1. HB288064MM1 Width CSD-slice Value 5 ...
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... The value for the asynchronous delay for the HB288064MM1 is 1 ms. The coded TAAC value is 0x0E (= 1 ms). For more details refer to Chapter “Operating Characteristics”. NSAC Defines the worst case for the synchronous data access time. N where NSAC presents a binary value. Max. value for the data access time N total access time is the sum of both TAAC and N HB288064MM1 is 0x01 (100 cycles). For more details refer to Chapter “ ...
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... For command class definition refer to Table “HB288064MM1 Command Classes”. Supported Card Command Classes CCC bit Supported card command classes 0 class0 1 class1 ...... ...... 11 class11 The HB288064MM1 supports the command classes and 7. The parameter CCC is permanently assigned to the value 0x0FF. HB288064MM1 13 ...
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... All block lengths between one and this value are permitted. The actual block size is programmed by the command SET_BLOCKLEN (CMD16). The HB288064MM1 supports block lengths from 1 byte up to 2048 bytes. The parameter READ_BLK_LEN is permanently assigned to the value 0x9. ...
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... Therefore, the maximal capacity which can be coded is 4096*512*512 = 1 GBytes. Example MBytes card with BLOCK_LEN = 512 can be coded with C_SIZE_MULT = 4 and C_SIZE = 1959. The card capacity is 64 MBytes. The value of the parameter C_SIZE used in the formula above for the HB288064MM1 is 0x7A7 (READ_BLK_LEN 12) ...
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... HB288064MM1 VDD_R_CURR_MIN, VDD_W_CURR_MIN The maximum supply current at the minimum supply voltage V Maximum Supply Current Consumption at V VDD_R_CURR_MIN VDD_W_CURR_MIN Code for current consumption at 2 0 100 mA The parameter VDD_R_CURR_MIN and VDD_W_CURR_MIN are permanently assigned to the value 5 (35 mA) ...
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... The card capacity is 64 MBytes. The value of the parameter C_SIZE_MULT used in the formula to calculate the card capacity (refer to parameter “C_SIZE”) for the HB288064MM1 is 4 (multiplier = 64). SECTOR_SIZE The size of an erasable or write protection sector. The content of this register is a binary coded value defining the number of write blocks (refer to “ ...
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... All block lengths between one and this value are permitted. The actual block size is programmed by the command SET_BLOCKLEN (CMD16). The HB288064MM1 supports blocks with the length 512 bytes. The parameter WRITE_BLK_LEN is permanently assigned to the value 0x9. ...
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... WRITE_BLK_PARTIAL = 1 means that smaller blocks can be used as well. The minimum block size will be equal to minimum addressable unit (one byte). The HB288064MM1 supports no partial block write. The parameter WRITE_BLK_PARTIAL is permanently assigned to the value ‘0’. FILE_FORMAT_GRP Indicates the selected group of file formats. This field is read-only for ROM. The usage of this field is shown in table “ ...
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... The content provider or customer defines which kind of error correction may be used to protect the contents of the HB288064MM1. This value is programmable. CRC The CRC register contains the check sum for the CSD content. The check sum is computed by the following formulas: Generator polynomial: ...
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... All communication between host and cards is controlled by the host (master). The host sends commands and, depending on the command, receives a corresponding response from the selected card. In this chapter the commands to control the HB288064MM1, the card responses and the contents of the status and error field included in the responses, are defined. ...
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... HB288064MM1 MultiMediaCard Each WP-group may have an additional write protection bit. The write protection bits are programmable via special commands (refer to Chapter “Commands”). Both functions are optional and only useful for writable/erasable devices. The write protection may also be useful for multi type MultiMediaCards (e.g. a ROM - Flash combination) ...
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... Commands The command set of the MultiMediaCard system is divided into classes corresponding to the type of card (see also [1]). The HB288064MM1 supports the following command classes: HB288064MM1 Command Classes (Class 0 to Class 2) Card command class (CCC) Class description Class 0 basic Class 1 stream read Class 2 ...
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... The command field contains the binary coded command number. The argument depends on the command (refer to Table “Basic Commands (class 0) and Table “Block-Oriented Read Commands (class 2)”). The CRC field is defined in Chapter “Cyclic Redundancy Check (CRC)”. The HB288064MM1 supports the following MultiMediaCard commands: 24 bit5...bit0 bit31 ...
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... The typical access and program times are defined as follows: Read The read access time is defined as the sum of the two times given by the CSD parameters TAAC and NSAC (refer to Table “Card Specific Data (CSD)”). These card parameters define the typical delay between the end bit Write Erase HB288064MM1 25 ...
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... HB288064MM1 Basic Commands (class 0) and Read Stream Command (class 1) CMD index Type Argument CMD0 bc [31:0] stuff bits CMD1 bcr [31:0] OCR without busy CMD2 bcr [31:0] stuff bits CMD3 ac [31:16] RCA [15:0] stuff bits CMD4 bc [31:16] DSR [15:0] stuff bits CMD7 ac [31:16] RCA [15:0] stuff bits CMD9 ac [31:16] RCA [15:0] stuff bits ...
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... Programming of the card identification register. This command is only done once per MultiMediaCard card. The card has some hardware to prevent this operation after the first programming. Normally this command is reserved for the manufacturer. R1 PROGRAM_CSD Programming of the programmable bits of the CSD. HB288064MM1 ...
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... HB288064MM1 Erase Commands (class 5) CMD index Type Argument CMD32 ac [31:0] data address CMD33 ac [31:0] data address CMD34 ac [31:0] data address CMD35 ac [31:0] data address CMD36 ac [31:0] data address CMD37 ac [31:0] data address CMD38 ac [31:0] stuff bits Write Protection Commands (class 6) CMD index Type Argument CMD28 ac [31:0] data address CMD29 ac ...
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... Lock Card Command (class 7) CMD index Type Argument CMD42 adtc [31:0] stuff bits Resp Abbreviation Command description R1b LOCK_UNLOCK used to set/reset the password or lock/unlock the card. The size of the data block is set by the SET_BLOCK_LEN command. HB288064MM1 29 ...
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... HB288064MM1 Card identification mode All the data communication in the card identification mode uses only the command line (CMD). Power on Idle state (idle) card is busy or host omitted voltage range CMD1 card looses bus Ready state (ready) CMD2 Indentification state (ident) CMD3 Stand-by state ...
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... The MultiMediaCard standards operating range validation is intended to support reduced voltage range MultiMediaCards. The HB288064MM1 supports the range of 2 3.6V supply voltage. So the HB288064MM1 sends a R3 response to CMD1 which contains an OCR value of 0x80FF8000 if the busy flag is set to “ready” or 0x00FF8000 if the busy flag is active (refer to Chapter “Responses”). By omitting the voltage range in the command, the host can query the card stack and determine the common voltage range before sending out-of-range cards into the Inactive State ...
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... Disconnect state (dis) HB288064MM1 State Diagram (Data Transfer Mode) The command SELECT_DESELECT_CARD (CMD7) is used to select one card and place it in the Transfer State previously selected card is in the Transfer State its connection with the host is released and it will move back to the Stand-by State. Only one card can be, at any time, in the Transfer State. A selected card is responding the CMD7, the deselected one does not respond to this command. When CMD7 is sent including the reserved relative card address “ ...
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... Receive-data-State) for a stop command. The write operation shall also be aborted if the host tries to write over a write-protected area. In this case, however, the card shall set the WP_VIOLATION bit. READ_BL_LEN -NSAC)/TAAC), If partial blocks are allowed (if CSD parameter WRITE_BL_LEN -NSAC)/(TAAC*R2W_FACTOR)), HB288064MM1 33 ...
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... In this case, however, the card will set the WP_VIOLATION bit. Programming of the CID and CSD register does not require a previous block length setting. The transferred data is also CRC protected. The HB288064MM1 write operation follows some special rules: Write to erased cells is done without automatic erase ...
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... LOCK/UNLOCK Locks the card Unlock the card (note that it is valid to set this bit together with SET_PWD but it is not allowed to set it together with CLR_PWD). CLR_PWD Clears PWD. SET_PWD Set new password to PWD PWD_LEN: Defines the following password length (in bytes). Bit5 Bit4 Bit3 Bit2 ERASE LOCK_ UNLOCK HB288064MM1 Bit1 Bit0 CLR_ SET_ PWD PWD 35 ...
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... HB288064MM1 PWD: The password (new or currently used depending on the command). The data block size shall be defined by the host before it sends the card lock/unlock command. This will allow different password sizes. The following paragraphs define the various lock/unlock command sequences: Setting the Password — ...
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... If the command was accepted then ALL THE CARD CONTENT WILL BE ERASED including the PWD and PWD_LEN register content and the locked card will get unlocked. LOCK_UNLOCK_FAILED error bit will be set in the status register. An attempt to force erase on an unlocked card will fail and HB288064MM1 37 ...
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... HB288064MM1 State transition summary Table “Card State Transition Table” defines the card state transitions as a function of received command Card State Transition Table Current state Command idle 1 CRC fail —* Commands out of the — supported class(es) Class0 CMD0 idle CMD1, card V ...
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... HB288064MM1 rcv prg dis ina rcv — — rcv — — — — — — — — — — — — ...
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... The OCR is sent as a response to the CMD1 to signalize the supported voltage range. The HB288064MM1 supports the range from 2 3.6 V. Respectively the value of all bits of the OCR field of the HB288064MM1 is set to 0x80FF8000. So the R3 frame of the HB288064MM1 contains the value 0x3F80FF8000FF if the card is ready and 0x3F00FF8000FF if the card is busy ...
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... X: Detected and set during command execution. The host must poll the card by sending status command in order to read these bits. Clear Condition: A: According to the card state. B: Always related to the previous command. Reception of a valid command will clear it (with a delay of one command). C: Clear by read. HB288064MM1 41 ...
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... HB288064MM1 Status Bits Identifier Type Value 31 OUT_OF_RANGE ADDRESS_ERROR ’0’= no error 29 BLOCK_LEN_ERRO ERASE_SEQ_ERR ERASE_PARAM WP_VIOLATION ’0’= not protected 25 CARD_IS_LOCKED LOCK_UNLOCK_ ’0’= no error FAILED 23 COM_CRC_ERROR ILLEGAL_COMMAN CARD_ECC_FAILE ...
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... Permanently 0 ’0’= disabled The card will expect ACMD or ’1’= enabled indication that the command has been interpreted as ACMD. Permanently 0 HB288064MM1 Clear Condition ...
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... Z-bit is driven to (respectively kept) HIGH by the pull-up resistors R respectively R . Actively driven P-bits are less sensitive to noise superposition. For the CMD DAT timing of the HB288064MM1, the following values are defined: Timing Values Value [clock cycles] Symbol Min N ...
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... Card active N cycles Response CR CRC Card active N cycles ID CRC Card active N cycles RC CRC HB288064MM1 content CRC content CRC clock cycles. ID CID or OCR content Host command content CRC E Host active 45 ...
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... HB288064MM1 Last host command - next host command timing diagram After the last command, which does not force a response, has been sent, the host can continue sending the next command after at least N clock periods. CC Host command CMD S T content Host active Timing CMD ...
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... The Card response S T content CRC E Card active CRC status Card busy status E S busy = 'L' Card active HB288064MM1 N WR Write data content Host active ...
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... HB288064MM1 Stream write The data transfer starts N clock cycles after the card response to the sequential write command was WR received. The bus transaction is identical to that of a write block command (see Figure “Timing of The Block Write Command”). As the data transfer is not block-oriented, the data stream does not include the CRC checksum ...
Page 49
... Reset GO_IDLE_STATE (CMD0) is the software reset command, which sets the HB288064MM1 into the Idle State independently of the current state. In the Inactive State the HB288064MM1 is not affected by this command. After power-on the HB288064MM1 is always in the Idle State. After power-on or command GO_IDLE_STATE (CMD0) all output bus drivers of the HB288064MM1 high-impedance state and the card will be initialized with a default relative card address (“ ...
Page 50
... HB288064MM1 SPI Communication The SPI mode consists of a secondary communication protocol. MultiMediaCard protocol, designed to communicate with a SPI channel, commonly found in Motorola’s (and lately a few other vendors’) microcontrollers. The interface is selected during the first reset command after power up (CMD0) and cannot be changed once the part is powered on. The SPI standard defines the physical link only, and not the complete data transfer protocol ...
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... Instead, a special data error token will be sent to the host. Figure “Read Operation-Data Error” shows a data read operation which terminated with an error token rather than a data block. from data from card card to host to host response data block CRC Read Operation HB288064MM1 Next commnand command 51 ...
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... HB288064MM1 from host to card Data in command Data out Data Write Overview As for the read operation, while in SPI mode the MultiMediaCard supports single block write commands only. Upon reception of a valid write command (CMD24 in the MultiMediaCard protocol), the card will respond with a response token and will wait for a data block to be sent from the host. CRC suffix, block length and start address restrictions are (with the exception of the CSD parameter WRITE_BL_PARTIAL controlling the partial block write option) identical to the read operation (refer to Figure “ ...
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... Data’ Operations HB288064MM1 from card to host response busy ) is used for read CR 53 ...
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... HB288064MM1 Error Conditions Unlike the MultiMediaCard protocol, in the SPI mode the card will always respond to a command. The response indicates acceptance or rejection of the command. A command may be rejected not supported (illegal opcode), if the CRC check failed contained an illegal operand was out of sequence during an erase sequence ...
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... R2 SEND_STATUS asks the selected card to send its status register. SET_BLOCKLEN selects a block length (in bytes) for all following block commands (read and write).* R1 READ_SINGLE_ reads a block of the size selected by BLOCK the SET_BLOCKLEN command.* HB288064MM1 ...
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... HB288064MM1 CMD index SPI mode Argument CMD24 Yes [31:0] data address CMD25 No CMD26 No CMD27 Yes None CMD28 Yes [31:0] data address CMD29 Yes [31:0] data address CMD30 Yes [31:0] write protect data address CMD31 reversed CMD32 Yes [31:0] data address CMD33 Yes [31:0] data address CMD34 Yes ...
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... The size of the Data Block is defined by the SET_BLOCK_LEN command. R3 READ_OCR Reads the OCR register of a card. R1 CRC_ON_OFF Turns the CRC option on or off. A ‘1’ in the CRC option bit will turn the option on, a ‘0’ will turn it off HB288064MM1 57 ...
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... HB288064MM1 Responses There are several types of response tokens the MultiMediaCard mode, all are transmitted MSB first: Format R1 This response token is sent by the card after every command with the exception of SEND_STATUS commands one byte long, and the MSB is always set to zero. The other bits are error indications, an error being signaled by a ‘ ...
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... CC error card ecc failed wp violation erase param out of range in idle state erase reset illegal command com crc error erase sequence error address error parameter error R2 Response Format | lock/unlock command failed: This status bit has two functions HB288064MM1 59 ...
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... HB288064MM1 Format R3 This response token is sent by the card when a READ_OCR command is received. The response length is 5 bytes (refer to Figure “R3 Response Format”). The structure of the first (MSB) byte is identical to response type R1. The other four bytes contain the OCR register Data Response Every data block written to the card will be acknowledged by a data response token ...
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... If a read operation fails and the card cannot provide the required data, it will send a data error token instead. This token is one byte long and has the following format The 4 least significant bits (LSB) are the same error bits as in the response format R2. 0 Error CC Error Card ECC failed out of range Data Error Token HB288064MM1 61 ...
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... HB288064MM1 SPI Bus Timing All timing diagrams use the following schematics and abbreviations: H: Signal is high (logical ‘1’) L: Signal is low (logical ‘0’) X: Don’t care Z: High impedance state (-> Repeater Busy: Busy Token Command: Command token Response: Response token Data block: Data token All timing values are defined in Table “ ...
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... card response Data block N CR Card response HB288064MM1 Data block ...
Page 64
... The HB288064MM1 is free of static errors. All errors are covered inside the card, even errors occurring during the livetime of HB288064MM1 are covered for the user. The only effect which may be notified by the end user is, that the overall memory capacity may be reduced by small number of blocks. All flash handling is done on card, so that no external error correction is needed ...
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... CRC[6...0] = Remainder [(M( One CRC is checked in the HB288064MM1 for every command. For each response a CRC is generate in the HB288064MM1. Each data block read from the HB288064MM1 will be succeeded by redundancy bits generated with the second CRC. The code is usable for payload lengths 2048 Bytes: ...
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... HB288064MM1 Power Supply Power Supply Decoupling The and V lines supply the card with operating voltage. For this, decoupling capacitors for SS1 SS2 CC buffering current peak are used. These capacitors are placed on the bus side corresponding to Figure “Power Supply Decoupling”. ...
Page 67
... A power on reset is generated on chip as long as V parser of the HB288064MM1 works properly but the access to the memory core is not guaranteed the power up phase (or when the HB288064MM1 is inserted during power up) the host has to wait after sending SEND_OP_COND (CMD1) for the identification delay before the ALL_SEND_CID (CMD2) can ...
Page 68
... HB288064MM1 3.6 V Bus master supply voltage 2.7 V 2.0 V Power up time Supply ramp up time Initialization sequence Initialization delay: The maximum of 1 msec, 74 clock cycles and supply ramp up time After power up (including hot insertion, i.e. inserting a card when the bus is operating) the MultiMediaCard enters the idle state. During this state the MultiMediaCard ignores all bus transactions until CMD1 is received ...
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... Short Cut Protection The HB288064MM1 can be inserted/removed into/from the bus without damage. If one of the supply pins ( not connected properly, then the current is drawn through a data line to supply the card Naturally the card can not operate properly under this conditions. ...
Page 70
... Storage temperature Operating temperature Junction temperature Electrical Characteristics In this chapter the electrical characteristics for the HB288064MM1 are defined in three steps: Pad characteristics: properties of the external connectors Absolute maximum ratings: if exceeded the card may be damaged Recommended operating conditions: characterization model of the environment of the ...
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... Min Max R 4.7 100 CMD R 50 100 DAT C — 250 L C — 100 L C — 7 CARD — 16 HB288064MM1 Unit Remark Human body model V max ( max ( short cut protected mA short cut protected Unit Remark k to prevent bus floating k to prevent bus floating ...
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... HB288064MM1 Recommended Operating Conditions The recommended operating conditions define the parameter ranges for optimal performance and durability of the HB288064MM1. Parameter Supply voltage Inputs Low-level input current V High-level input current V Outputs High-level output current Low-level output current Clock Clock frequency data 1 input clk* transfer mode (pp) Clock frequency ident ...
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... SCLK) Output hold time Symbol Min Typ Max 45 150 – 0.75V 0.125V ISU OSU HB288064MM1 Unit Remark MHz, 3 Hz, 3.6 V stby state min max ...
Page 74
... AAD The synchronous part of the access time is sum of the command frame length and some additional internal cycles ( cycles MHz one cycle (1/f SAD time 0.8 s. The asynchronous access delay of the HB288064MM1 is T SAD The resulting memory access time ...
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... Symbol Typ Max Unit N — 16 cycles SAD T — 0.8 s SAD T 300 — s AAD 1 t 300.8 — (maximum: 16 cycles) by division with 100 SAD HB288064MM1 Remark at 20 MHz clock frequency at 20 MHz clock frequency 75 ...
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... HB288064MM1 Abbreviations and Terms Abbreviations Terms <n> Argument of a command or data field. CMD<n> MultiMediaCard bus command <n>. See Command. PP Push Pull, output driver type with low impedance driver capability for 0 and 1. OD Open Drain, output driver type with low impedance driver capability for 0 and high impedance driver capability for 1 ...
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... Number of synchronous access cycles to be added to the access delay f Open drain mode operating frequency (maximum 400kHz Push pull mode operating frequency (maximum 20MHz). PP MSB Most significant bit. LSB Least significant bit. Human Body Model Standard model to simulate electrical conditions induced by handling and touching of electrical devices by humans. HB288064MM1 77 ...
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... HB288064MM1 Physical Outline 24.00 3 – R1.00 19.75 1. – R0.5 4.00 4.00 21.8 1.1 0.08 4 – R1.0 0.90 Front + 0.2 – 0.1 + 0.2 4.75 – 0.1 + 0.1 3.0 – 0.2 2.50 Back Unit: mm Tolerance: 0.1 mm 1.4 1.32 ...
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... Telex: 40815 HITEC HX Hitachi Asia Ltd. Taipei Branch Office 3rd Flr, Hung Kuo Building, No.167, Tun Hwa North Road, Taipei (105) Taiwan Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Telex: 23222 HAS-TP Copyright © Hitachi, Ltd., 2000. All rights reserved. Printed in Japan. HB288064MM1 Colophon 1.0 79 ...