mt18vddf12872g-265 Micron Semiconductor Products, mt18vddf12872g-265 Datasheet - Page 9

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mt18vddf12872g-265

Manufacturer Part Number
mt18vddf12872g-265
Description
512mb, 1gb X72, Ecc, Sr 184-pin Ddr Sdram Rdimm
Manufacturer
Micron Semiconductor Products
Datasheet
I
Table 9:
PDF: 09005aef8074e85b/Source: 09005aef8072fe49
DDF18C64_128x72.fm - Rev. E 6/08 EN
Parameter/Condition
Operating one bank active-precharge current:
t
Address and control inputs changing once every two clock cycles
Operating one bank active-read-precharge current: BL = 2;
t
changing once per clock cycle
Precharge power-down standby current: All device banks idle; Power-
down mode;
Idle standby current: CS# = HIGH; All device banks idle;
CKE = HIGH; Address and other control inputs changing once per clock cycle;
V
Active power-down standby current: One device bank active; Power-
down mode;
Active standby current: CS# = HIGH; CKE = HIGH; One device bank active
t
per clock cycle; Address and other control inputs changing once per clock
cycle
Operating burst read current: BL = 2; Continuous burst reads; One device
bank active; Address and control inputs changing once per clock cycle;
t
Operating burst write current: BL = 2; Continuous burst writes; One
device bank active; Address and control inputs changing once per clock
cycle;
cycle
Auto refresh current
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device bank interleaving
reads (BL = 4) with auto precharge;
Address and control inputs change only during active READ or WRITE
commands
DD
CK =
RC =
RC =
CK =
IN
= V
Specifications
t
t
t
t
t
RC (MIN);
CK (MIN); DQ, DM, and DQS inputs changing once per clock cycle;
RAS (MAX);
CK (MIN); I
CK =
REF
for DQ, DM, and DQS
t
CK (MIN); DQ, DM, and DQS inputs changing twice per clock
t
t
I
Values are shown for the MT46V64M4 DDR SDRAM only and are computed from values specified in the
256Mb (64 Meg x4) component data sheet
CK =
CK =
DD
t
CK =
OUT
Specifications and Conditions – 512MB
t
t
t
CK =
CK (MIN); CKE = LOW
CK (MIN); CKE = LOW
= 0mA
t
CK (MIN); I
t
CK (MIN); DQ, DM, and DQS inputs changing twice
OUT
t
RC =
= 0mA; Address and control inputs
t
RC (MIN);
512MB, 1GB (x72, ECC, SR) 184-Pin DDR SDRAM RDIMM
t
RC =
t
CK =
t
t
REFC =
REFC = 7.8125µs
t
RC (MIN);
t
t
CK =
CK (MIN);
9
t
RFC (MIN)
t
CK (MIN);
Micron Technology, Inc., reserves the right to change products or specifications without notice.
;
Symbol
I
I
I
I
I
I
I
DD
DD
DD
I
I
DD
I
I
I
DD
DD
DD
DD
DD
DD
DD
DD
4W
3N
5A
4R
2P
2F
3P
0
1
5
6
7
2,430
3,060
1,080
1,260
3,600
3,510
4,680
8,460
Electrical Specifications
-40B
720
108
72
72
©2003 Micron Technology, Inc. All rights reserved.
2,250
3,060
1,080
3,150
3,150
4,590
7,380
-335
900
540
108
72
72
2,160
2,610
2,700
2,700
4,410
6,570
-265
810
540
900
108
72
72
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA

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