mt8vddt6464hg-40b Micron Semiconductor Products, mt8vddt6464hg-40b Datasheet
mt8vddt6464hg-40b
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mt8vddt6464hg-40b Summary of contents
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... Address Table Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing pdf: 09005aef80b577e4, source: 09005aef80921669 DDA8C32_64x64HG.fm - Rev. D 9/04 EN PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 256MB, 512MB (x64, SR) PC3200 200-PIN DDR SODIMM MT8VDDT3264H – ...
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... MT8VDDT6464HG-40B__ 512MB MT8VDDT6464HY-40B__ 512MB NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT8VDDT6464HG-40BA1. pdf: 09005aef80b577e4, source: 09005aef80921669 DDA8C32_64x64HG.fm - Rev. D 9/04 EN 256MB, 512MB (x64, SR) PC3200 CONFIGURATION MODULE BANDWIDTH 32 Meg ...
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... DD DQ41 195 SCL 46 DQS5 197 V 48 DDSPD V 199 Figure 2: Module Layout Back View PIN 199 PIN 200 Indicates pin Indicates DDQ Micron Technology, Inc., reserves the right to change products or specifications without notice. 3 200-PIN DDR SODIMM ...
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Table 5: Pin Descriptions Pin numbers may not correlate with symbols. Refer to Pin Assignment tables on page 3 for more information PIN NUMBERS 118, 119, 120 WE#, CAS#, RAS# 35, 37, 158, 160 CK0, CK0#, CK1, CK1#, 96 121 ...
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... SS V Supply Serial EEPROM positive power supply: +2.3V to +3.6V. DDSPD DNU — Do Not Use: These pins are not connected on these modules, but are assigned pins on other modules in this product family. NC — No Connect: These pins should be left unconnected. 5 200-PIN DDR SODIMM DESCRIPTION Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... SERIAL PD SCL SA0 SA1 SA2 Standard modules use the following DDR SDRAM devices: MT46V32M8TG (256MB); MT46V64M8TG (512MB) www.micron.com/ Lead-free modules use the following DDR SDRAM devices: MT46V32M8P (256MB); MT46V64M8P (512MB) 6 200-PIN DDR SODIMM DM1 DM CS# DQS DQ8 DQ DQ9 DQ DQ10 DQ 3 ...
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... I/O pins. A single read or write access for the DDR SDRAM module effec- tively consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corre- sponding n-bit wide, one-half-clock-cycle data trans- fers at the I/O pins ...
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Burst Length Read and write accesses to DDR SDRAM devices are burst oriented, with the burst length being program- mable, as shown in Figure 4, Mode Register Definition Diagram. The burst length determines the maximum number of column locations that ...
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Table 6: Burst Definition Table STARTING BURST COLUMN ORDER OF ACCESSES LENGTH ADDRESS WITHIN A BURST TYPE = SEQUENTIAL 0 0-1-2 1-2-3 2-3-0 3-0-1-2 ...
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The extended mode register must be loaded when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements could result in ...
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Commands Table 8, Commands Truth Table, and Table 9, DM Operation Truth Table, provide a general reference of available commands. For a more detailed description Table 8: Commands Truth Table CKE is HIGH for all commands shown except SELF REFRESH; ...
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Absolute Maximum Ratings Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- ...
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Table 12: I Specifications and Conditions – 256MB DD DDR SDRAM component values only Notes: 1–5, 8, 10, 12, 47; notes appear on pages 17–19; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge ...
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Table 13: I Specifications and Conditions – 512MB DD DDR SDRAM component values only Notes: 1–5, 8, 10, 12, 47; notes appear on pages 17–19; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge ...
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Table 14: Capacitance Note: 11; notes appear on pages 17–19 PARAMETER Input/Output Capacitance: DQ, DQS, DM Input Capacitance: Command and Address, S#, CKE Input Capacitance: CK, CK# Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions Notes: ...
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Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (Continued) Notes: 1–5, 12-15, 29; notes appear on pages 17–19; 0°C AC CHARACTERISTICS PARAMETER ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read ...
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Notes 1. All voltages referenced Tests for AC timing and electrical AC and DC DD characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device operation are ...
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DRAM controller greater than eight refresh cycles is not allowed. 22. The valid data window is derived by achieving t t other specifications CK/2 ...
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... DLL is required to be reset. This is followed by 200 clock cycles (before READ commands). 46. Leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. 47. When an input signal is HIGH or LOW defined as a steady state logic HIGH or LOW. ...
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Initialization To ensure device operation the DRAM must be ini- tialized as described below: 1. Simultaneously apply power Apply V and then V power. REF TT 3. Assert and hold CKE at a LVCMOS logic low. 4. ...
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SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 10, Data Validity, and Figure ...
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Table 16: EEPROM Device Select Code Most significant bit (b7) is sent first SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code Table 17: EEPROM Operating Modes MODE Current Address Read Random Address Read Sequential Read Byte ...
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Table 18: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced DDSPD PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE 3mA ...
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... Fundamental Memory Type 3 Number of Row Addresses on Assembly 4 Number of Column Addresses on Assembly 5 Number of Physical Ranks on DIMM 6 Module Data Width 7 Module Data Width (Continued) 8 Module Voltage Interface Levels ( SDRAM Cycle Time, ( CK) CAS Latency = 3 10 SDRAM Access From Clock ( 11 Module Configuration Type 12 Refresh Rate/type 13 ...
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... DIMM Height 48–61 Reserved 62 SPD Revision 63 Checksum for Bytes 0-62 64 Manufacturer’s JEDEC ID Code 65-71 Manufacturer’s JEDEC IDCode 72 Manufacturing Location 73-90 Module Part Number (ASCII) 91 PCB Identification Code 92 Identification Code (Continued) 93 Year of Manufacture in BCD 94 Week of Manufacturein BCD 95-98 Module Serial Number 99-127 Manufacturer-specific Data (RSVD) pdf: 09005aef80b577e4, source: 09005aef80921669 DDA8C32_64x64HG ...
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Figure 14: 200-Pin DDR SODIMM Dimensions 0.079 (2.00) R (2X) U1 0.071 (1.80) (2X) 0.236 (6.00) 0.096 (2.44) 0.079 (2.00) 0.039 (0.99) TYP U8/U5 PIN 200 NOTE: 1. Numbers indicate beveled PCB/non-beveled PCB. 2. All dimensions are in inches (millimeters); ...