k9f1216u0a-ycb0 Samsung Semiconductor, Inc., k9f1216u0a-ycb0 Datasheet
k9f1216u0a-ycb0
Available stocks
Related parts for k9f1216u0a-ycb0
k9f1216u0a-ycb0 Summary of contents
Page 1
ELECTRONICS March. 2003 512Mb/256Mb 1.8V NAND Flash Errata Description : Some of AC characteristics are not meeting the specification > AC characteristics : Refer to Table Affected Products : K9F1208Q0A-XXB0, K9F1216Q0A-XXB0 K9F5608Q0C-XXB0, K9F5616Q0C-XXB0 K9K1208Q0C-XXB0, K9K1216Q0C-XXB0 Improvement schedule : The components ...
Page 2
... The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you. K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 15 25 ...
Page 3
... K9F12XXX0A s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9F12XXX0A is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility. K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 Vcc Range Organization 1.70 ~ 1.95V X16 2 ...
Page 4
... N.C CLE CLE ALE ALE N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C PACKAGE DIMENSIONS 48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE( TSOP1 - 1220F #1 #24 ¡Æ 0~8 0.45~0.75 0.018~0.030 K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 K9F12XXU0A-YCB0,PCB0/YIB0,PIB0 20.00 0.20 0.787 ...
Page 5
... A /WP ALE Vss / /RE CLE I/ I/O1 NC VccQ I/O5 H Vss I/O2 I/O3 I/O4 N.C N.C N.C N.C Top View K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 K9F12XXX0A-DCB0,HCB0/DIB0,HIB0 5 6 N.C N.C N.C N.C N.C N.C N.C A /WE R Vcc G I/O7 H I/O6 Vss N.C N.C N.C N.C N.C N.C N.C N.C 4 FLASH MEMORY X16 ...
Page 6
... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 63-Ball TBGA (measured in millimeters) Top View 8.50 0.10 #A1 0.10MAX K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 6 (Datum (Datum 63- 0.45 0.05 0. Side View 15.00 0.10 5 FLASH MEMORY Bottom View #A1 INDEX MARK(OPTIONAL) 8.50 A 0.10 0. 7.20 0. 4.00 0. 2.00 0.45 0.05 B ...
Page 7
... R DNU N.C Vcc Vss N.C DNU CLE ALE WE WP N.C N.C DNU N.C N.C PACKAGE DIMENSIONS 48-PIN LEAD/LEAD FREE PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE ( WSOP1 - 1217F #1 #24 K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-VCB0,FCB0/VIB0,FIB0 ...
Page 8
... CC Vss GROUND NO CONNECTION N.C Lead is not internally connected. DO NOT USE DNU Leave it disconnected. NOTE : Connect all V and V pins of each device to common power supply outputs not leave disconnected K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 Pin Function 7 FLASH MEMORY ...
Page 9
... Command(Read) : Defines the starting address of the 2nd half of the register set to "Low" or "High" by the 00h or 01h Command must be set to "Low". * The device ignores any additional input of address cycles than reguired. K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 (512 + 16)Byte x 131072 Page Register & S Register I/O Buffers & ...
Page 10
... Cycle 3rd Cycle 4th Cycle NOTE : Column Address : Starting Address of the Register must be set to "Low". K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 (256 + 8)Word x 131072 Page Register & S/A Register I/O Buffers & Latches Global Buffers WP 8 Word I I Word I/O 2 I/O 3 I ...
Page 11
... Page Program(Dummy) and Copy-Back Program(Dummy) are available on the 2nd,3rd,4th plane of multi plane operation. 3. The 71h command should be used for read status of Multi Plane operation. Caution : Any undefined command inputs are prohibited except for above command set of Table 1. K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 1st. Cycle 2nd. Cycle ...
Page 12
... Block 4 Page 0 Page 1 Page 30 Page 31 Block 4088 Page 0 Page 1 Page 30 Page 31 Block 4092 Page 0 Page 1 Page 30 Page 31 528byte Page Registers K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 Plane 2 Plane 1 (1024 Block) (1024 Block) Block 2 Block 1 Page 0 Page 1 Page 30 Page 31 Block 6 Block 5 Page 0 Page 1 Page 30 Page 31 ...
Page 13
... Input High Voltage V IH Input Low Voltage, All inputs V IL Output High Voltage Level V OH Output Low Voltage Level V OL Output Low Current(R/B) I (R/B) OL K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 Symbol K9F12XXQ0A(1.8V) V IN/OUT CCQ T BIAS T STG Ios +0.3V which, during transitions, may overshoot to V CC, ...
Page 14
... WP should be biased to CMOS high or CMOS low for standby. Program / Erase Characteristics Parameter Program Time Dummy Busy Time for Multi Plane Program Number of Partial Program Cycles in the Same Page Block Erase Time K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 Symbol Min N 4,026 VB K9F12XXQ0A 0V to VccQ ...
Page 15
... If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us break the sequential read cycle, CE must be held high for longer time than tCEH. 3. The time to Ready depends on the value of the pull-up resistor tied R/B pin. K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 Symbol Min ...
Page 16
... Any intentional erasure of the original invalid block information is prohibited. Increment Block Address Create (or update) Invalid Block(s) Table Figure 4. Flow chart to create invalid block table. K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 Start Set Block Address = 0 Check "FFh" at the column address * 517(X8 device) or 256 and 261(X16 device) ...
Page 17
... Read Status Register I R Program Error I K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 Detection and Countermeasure sequence Status Read after Erase --> Block Replacement Status Read after Program --> Block Replacement Read back ( Verify after Program) --> Block Replacement Verify ECC -> ECC Correction program operation results in an error, map out ...
Page 18
... Step3 Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ’ B’ Step4 Do not further erase Block ’ A’ by creating an ’ invalid Block’ table or other appropriate scheme. K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 Read Flow Chart No Reclaim the Error Yes ...
Page 19
... Command input sequence for programming ’ C’ area The address pointer is set to ’ C’ area(512~527), and sustained 50h 80h Only ’ C’ area can be programmed. K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 Area 1st half array(A) 2nd half array(B) spare array(C) Figure 5. Block Diagram of Pointer Operation ...
Page 20
... Command input sequence for programming ’ B’ area The address pointer is set to ’ B’ area(256~263), and sustained 50h 80h Only ’ B’ area can be programmed. K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 Area main array(A) spare array(B) Figure 6. Block Diagram of Pointer Operation Address / Data input ...
Page 21
... Figure 8. Read Operation with CE don’ t-care. CLE CE RE ALE R/B WE I/O X 00h Start Add.(4Cycle) K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 Data Input I K9F1208U0A-Y,P or K9F1208U0A-V,F CE must be held low during FLASH MEMORY CE don’ t-care Data Input ...
Page 22
... NOTE: 1. I/O8~15 must be set to "0" during command or address input. 2. I/O8~15 are used only for data bus. * Command Latch Cycle CLE CE WE ALE I Address Latch Cycle t CLS CLE ALS ALE I/O X K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 I/O I/ CLH CLS ALS ALH t t ...
Page 23
... K9F1208U0A-DCB0,DIB0,HCB0,HIB0 * Input Data Latch Cycle CLE CE t ALS ALE I/Ox * Serial access Cycle after Read R/B NOTES : Transition is measured 200mV from steady state voltage with load. K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 DIN 0 DIN 1 (CLE=L, WE=H, ALE=L) t ...
Page 24
... WC WE ALE RE N Address 00h or 01h I Column Address R/B X8 device : m = 528 , Read CMD = 00h or 01h X16 device : m = 264 , Read CMD = 00h K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 t CLR t CLS t CLH WHR 70h On K9F1208U0A-Y,P or K9F1208U0A-V,F CE must be held ...
Page 25
... CE WE ALE I/O 00h or 01h Column Address R/B Read2 Operation (Read One Page) CLE CE WE ALE RE I/O 50h R/B M Address K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 Page(Row) Address Busy ...
Page 26
... X R/B M Page Program Operation CLE ALE RE 80h I Sequential Data Column Input Command Address R/B K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 Dout Ready Busy N Output Din ~ 528 Byte Data ...
Page 27
... K9F1208U0A-DCB0,DIB0,HCB0,HIB0 BLOCK ERASE OPERATION CLE ALE RE I/O 60h Page(Row) Address R/B Auto Block Erase Setup Command K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 (ERASE ONE BLOCK DOh Erase Command 26 FLASH MEMORY t BERS 70h I/O 0 Busy I/O =0 Successful Erase 0 Read Status I/O =1 Error in Erase ...
Page 28
... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 27 FLASH MEMORY ...
Page 29
... Max. 4 times repeatable * For Multi-Plane Erase operation, Block address to be erased should be repeated before "D0H" command. Ex.) Four-Plane Block Erase Operation R/B I Address 60h 60h K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 DOh 24 25 Erase Confirm Command 60h 60h 9 25 ...
Page 30
... Byte ECh 2 nd Byte 76h 3 rd Byte A5h C0h 4 th Byte K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 t REA 00h ECh Address. 1cycle Maker Code Device Code Device K9F1208Q0A K9F1208U0A K9F1216Q0A K9F1216U0A Description Maker Code Device Code Must be don’ t -cared Supports Multi Plane Operation ...
Page 31
... ALE RE 00h I Column Page(Row) Address Address R/B K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 On K9F1208U0A-Y,P or K9F1208U0A-V,F CE must be held low during 8Ah Column Address Busy Copy-Back Data Input Command 30 FLASH MEMORY t t PROG ...
Page 32
... CE high. When the page address moves onto the next block, read command and address must be given. Figures 9, 10 show typical sequence and timings for sequential row read operation. K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 ). The system controller can detect the completion are ignored ...
Page 33
... X8 device : X16 device : NOTE: 1) After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle. K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 On K9F1208U0A-Y,P or K9F1208U0A-V,F CE must be held low during & & A ...
Page 34
... The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of a block is read- out, the sequential read operation must be terminated by bringing CE high. When the page address moves onto the next block, read command and address must be given. K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 On K9F1208U0A-Y,P or K9F1208U0A-V,F CE must be held low during tR ...
Page 35
... Read Status command mode until another valid command is written to the command register. Figure 11. Program & Read Status Operation R/B I 80h Address & Data Input & 528 Byte Data K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 Data Output 1st 25 Data Field Spare Field t PROG 10h ~ A 9 ...
Page 36
... Data Input Plane 0 (1024 Block) Block 0 Block 4 Block 4088 Block 4092 K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 valid while ignored. The Erase Confirm command(D0h) following the BERS D0h ~ DBSY Address & ...
Page 37
... Upon the erase completion, pass/fail status of each block is examined by reading extended pass/fail status(I/O 1 through I/O 4). Figure 17. Four Block Erase Operation R/B Address Address I/O 60h 60h X (3 Cycle) (3 Cycle & K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 Plane 2 Plane 1 (1024 Block) (1024 Block) Block 2 Block 1 Page 0 Page 1 Page 30 Page 31 Plane 0 80h 80h 11h t PROG 10h ~ A 9 ...
Page 38
... For this reason, two bit error correction is recommended for the use of Copy-Back operation." Figure 18. One Page Copy-Back program Operation R/B I/O Add.(4Cycles) X 00h & Source Address K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 t R Add.(4Cycles) 10h 8Ah & Destination Address 37 FLASH MEMORY ...
Page 39
... Block 4088 Block 4092 8Ah Destination Address Input Plane 0 (1024 Block) Block 0 Block 4 Block 4088 Block 4092 K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 Max Three Times Repeatable 03h 03h Plane 1 (1024 Block) Block 1 Block 5 Block 4089 Block 4089 Block 4093 Max Three Times Repeatable ...
Page 40
... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 39 FLASH MEMORY ...
Page 41
... I/O 0 describes combined Pass/Fail condition for all planes. If any of the selected multiple pages/blocks fails in Program/ NOTE : Erase operation, it sets "Fail" flag. 2. The pass/fail status applies only to the corresponding plane. K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 Definition by 70h Command Pass : "0" Fail : "1" ...
Page 42
... A5h must be don’ t-cared. C0h means that device supports Multi Plane operation. The command regis- ter remains in Read ID mode until further commands are issued to it. Figure 21 shows the operation sequence. Figure 21. Read ID Operation 1 CLE CE WE ALE RE I 90h Address. 1cycle K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 t CEA WHR t REA ECh 00h Maker code Device K9F1208Q0A ...
Page 43
... The R/B pin transitions to low for tRST after the Reset command is written. Refer to Figure 22 below. Figure 22. RESET Operation R/B I FFh Table5. Device Status Operation Mode K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 t RST After Power-up Read 1 42 FLASH MEMORY After Reset Waiting for next command ...
Page 44
... Rp(ohm) Rp value guidance Rp(min, 1.8V part) = Rp(min, 3.3V part) = where I Rp(max) is determined by maximum permissible limit of tr K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 Rp ibusy 1.8V device - V 3.3V device - V Ready Vcc Fig ,tf & ibusy = 30pF L 3m 300n 2m 200n 120 1m 100n ...
Page 45
... A recovery time of minimum required before internal cir- IL cuit gets ready for any command sequences as shown in Figure 24. The two step command sequence for program/erase provides additional software protection. Figure 24. AC Waveforms for Power Transition 1.8V device : ~ 1.5V 3.3V device : ~ 2. K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 High FLASH MEMORY 1.8V device : ~ 1.5V 3.3V device : ~ 2.5V ...