k9f1608w0a-tcb0 Samsung Semiconductor, Inc., k9f1608w0a-tcb0 Datasheet

no-image

k9f1608w0a-tcb0

Manufacturer Part Number
k9f1608w0a-tcb0
Description
2m X 8 Bit Nand Flash Memory
Manufacturer
Samsung Semiconductor, Inc.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
K9F1608W0A-TCB0
Manufacturer:
SIEMENS
Quantity:
2
Part Number:
K9F1608W0A-TCB0
Manufacturer:
SUMSUNG
Quantity:
16 494
K9F1608W0A-TCB0, K9F1608W0A-TIB0
Document Title
Revision History
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
Revision No.
2M x 8 Bit NAND Flash Memory
0.0
1.0
1.1
1.2
1.3
History
Initial issue.
Data Sheet 1998.
Data Sheet 1999.
1) Added CE don’ t care mode during the data-loading and reading
1) Revised real-time map-out algorithm(refer to technical notes)
Changed device name
- KM29W16000AT -> K9F1608W0A-TCB0
- KM29W16000AIT -> K9F1608W0A-TIB0
1
Draft Date
April 10th 1998
July 14th 1998
April 10th 1999
July 23th 1999
Sep.15th 1999
FLASH MEMORY
Remark
Preliminary
Final
Final
Final
Final

Related parts for k9f1608w0a-tcb0

k9f1608w0a-tcb0 Summary of contents

Page 1

... Revised real-time map-out algorithm(refer to technical notes) 1.3 Changed device name - KM29W16000AT -> K9F1608W0A-TCB0 - KM29W16000AIT -> K9F1608W0A-TIB0 The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you ...

Page 2

... K9F1608W0A-TCB0, K9F1608W0A-TIB0 Bit NAND Flash Memory FEATURES Voltage Supply : 2.7V ~ 5.5V Organization - Memory Cell Array : (2M + 64K)bit x 8bit - Data Register : (256 + 8)bit x8bit Automatic Program and Erase - Page Program : (256 + 8)Byte - Block Erase : (4K + 128)Byte - Status Register 264-Byte Page Read Operation - Random Access : 10 s(Max.) - Serial Page Access : 80ns(Min ...

Page 3

... K9F1608W0A-TCB0, K9F1608W0A-TIB0 Figure 1. FUNCTIONAL BLOCK DIAGRAM X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command Register CE Control Logic RE & High Voltage WE Generator CLE ALE WP Figure 2. ARRAY ORGANIZATION 16M : 8K Row (=512 Block) 256B Column Page Register 256Byte ...

Page 4

... K9F1608W0A-TCB0, K9F1608W0A-TIB0 PRODUCT INTRODUCTION The K9F1608W0A is a 16.5Mbit(17,301,504 bit) memory organized as 8192 rows by 264 columns. Spare eight columns are located from column address of 256 to 263. A 264-byte data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made cells that are serially connected to form a NAND structure ...

Page 5

... K9F1608W0A-TCB0, K9F1608W0A-TIB0 PIN DESCRIPTION Command Latch Enable(CLE) The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal. Address Latch Enable(ALE) The ALE input controls the path activation for address and input data to the internal address/data register ...

Page 6

... Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltage reference to GND, K9F1608W0A-TCB0 Parameter Symbol ...

Page 7

... K9F1608W0A-TCB0, K9F1608W0A-TIB0 VALID BLOCK Parameter Symbol Valid Block Number NOTE : K9F1608W0A 1. The may include invalid blocks. Invalid blocks are defined as blocks that contain one or more bad bits. Do not try to access these invalid blocks for program and erase. During its lifetime of 10 years and/or 1million program/erase cycles,the minimum number of valid blocks are guaranteed though its initial number could be reduced ...

Page 8

... K9F1608W0A-TCB0, K9F1608W0A-TIB0 AC Timing Characteristics for Command / Address / Data Input Parameter CLE Set-up Time CLE Hold Time CE Setup Time CE Hold Time WE Pulse Width ALE Setup Time ALE Hold Time Data Setup Time Data Hold Time Write Cycle Time WE High Hold Time AC Characteristics for Operation ...

Page 9

... K9F1608W0A-TCB0, K9F1608W0A-TIB0 NAND Flash Technical Notes Invalid Block(s) Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. Typically, an invalid block will contain a single bad bit. The information regarding the invalid block(s) is called as the invalid block information. ...

Page 10

... K9F1608W0A-TCB0, K9F1608W0A-TIB0 NAND Flash Technical Notes (Continued) Error in write or read operation Over its life time, the additional invalid blocks may occur. Through the tight process control and intensive testing, Samsung mini- mizes the additional block failure rate, which is projected below 0.1% up until 1million program/erase cycles. Refer to the qualification report for the actual data ...

Page 11

... K9F1608W0A-TCB0, K9F1608W0A-TIB0 NAND Flash Technical Notes (Continued) Erase Flow Chart Start Write 60H Write Block Address Write D0H Write 70H SR R Yes * No Erase Error SR Yes Erase Completed : If erase operation results in an error, map out * the failing block and replace it with another block. ...

Page 12

... K9F1608W0A-TCB0, K9F1608W0A-TIB0 System Interface Using CE don’ t -care. For a easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 256byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read- ing would provide significant savings in power consumption ...

Page 13

... K9F1608W0A-TCB0, K9F1608W0A-TIB0 * Command Latch Cycle CLE ALE I Address Latch Cycle CLE ALE I CLS CLH ALS ALH Command t CLS ALS FLASH MEMORY ...

Page 14

... K9F1608W0A-TCB0, K9F1608W0A-TIB0 * Input Data Latch Cycle CLE CE t ALS ALE I DIN 0 * Sequential Out Cycle after Read R/B NOTES : Transition is measured 200mV from steady state voltage with load DIN 255 ...

Page 15

... K9F1608W0A-TCB0, K9F1608W0A-TIB0 * Status Read Cycle CLE I READ1 OPERATION (READ ONE PAGE) CLE CE WE ALE RE I/O 00h Column Page(Row) Address Address R/B t CLS t t CLS CLH WHR 70H ...

Page 16

... K9F1608W0A-TCB0, K9F1608W0A-TIB0 READ1 OPERATION (INTERCEPTED BY CE) CLE CE WE ALE I/O 00h Column Page(Row) Address Address R/B READ2 OPERATION (READ ONE PAGE) CLE CE WE ALE RE 50H I R/B M Address Dout N Dout N Busy ...

Page 17

... K9F1608W0A-TCB0, K9F1608W0A-TIB0 SEQUENTIAL ROW READ OPERATION CLE CE WE ALE RE 00H I R/B M PAGE PROGRAM OPERATION CLE CE WE ALE RE 80H I Sequential Data Column Input Command Address R/B Dout Dout Dout N+1 N+2 Ready Busy M+1 N Output Din ...

Page 18

... K9F1608W0A-TCB0, K9F1608W0A-TIB0 BLOCK ERASE OPERATION CLE CE WE ALE RE I 60H Block Address R/B Auto Block Erase Setup Command MANUFACTURE & DEVICE ID READ OPERATION CLE CE WE ALE RE I/O ~ 90H 0 7 Read ID Command (ERASE ONE BLOCK BERS DOH 20 Busy Erase Command ...

Page 19

... K9F1608W0A-TCB0, K9F1608W0A-TIB0 DEVICE OPERATION PAGE READ Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00H to the command reg- ister along with three address cycles. Once the command is latched, it does not need to be written for the following page read opera- tion ...

Page 20

... K9F1608W0A-TCB0, K9F1608W0A-TIB0 Figure 4. Read2 Operation CLE CE WE ALE R/B RE 50H Start Add.(3Cycle) I & Don't Care) Figure 5. Sequential Row Read1 Operation R/B I 00H Start Add.(3Cycle & Busy(Seek Time) 20 Seek Time Data Field ...

Page 21

... K9F1608W0A-TCB0, K9F1608W0A-TIB0 Figure 6. Sequential Row Read2 Operation R/B I 50H Start Add.(3Cycle & Don't Care) PAGE PROGRAM The device is programmed basically on a page basis. But it also allows multiple partial page programming of a byte or consecutive bytes up to 264 may be programmed in a single page program cycle. The number of partial page programming operation in the same page without an intervening erase operation must not exceed ten ...

Page 22

... K9F1608W0A-TCB0, K9F1608W0A-TIB0 BLOCK ERASE The Erase operation is done on a block(4K Byte) basis. Block address loading is accomplished in two cycles initiated by an Erase Setup command(60H). Only address A 12 block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions ...

Page 23

... K9F1608W0A-TCB0, K9F1608W0A-TIB0 READ ID The device contains a product identification mode, initiated by writing 90H to the command register, followed by an address input of 00H. Two read cycles sequentially output the manufacture code(ECH), and the device code (EAH) respectively. The command reg- ister remains in Read ID mode until further commands are issued to it. Figure 9 shows the operation sequence. ...

Page 24

... K9F1608W0A-TCB0, K9F1608W0A-TIB0 READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg- ister or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied ...

Page 25

... K9F1608W0A-TCB0, K9F1608W0A-TIB0 PACKAGE DIMENSIONS 44(40) LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(II) 44(40) - TSOP2 - 400F #44(40) #1 18.81 Max. 0.741 18.41 0.10 0.725 0.004 0.805 0.35 0.10 0.032 0.014 0.004 FLASH MEMORY 0.25 0.010 #23(21) #22(20) 0.15 0.006 0.80 0.0315 25 Unit :mm/Inch 0~8 TYP 0.50 0.020 +0.10 -0.05 +0.004 -0.002 0.10 MAX 0.004 ...

Related keywords