hys64t128020edl-3s-c Qimonda, hys64t128020edl-3s-c Datasheet - Page 16

• Manufacturer Part Number: hys64t128020edl-3s-c
• Description: 200-pin So-dimm Ddr2 Sdram Modules Ddr2 Sdram So-dimm Sdram
• Manufacturer: Qimonda

2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
3) Inputs are not recognized as valid until
4) The output timing reference voltage level is
5)
3.3.2
Rev. 1.02, 2007-10
11212006-D34H-5W6Z
Parameter
CAS to CAS command delay
Average clock high pulse width
Average clock period
CKE minimum pulse width ( high and
low pulse width)
Average clock low pulse width
Auto-Precharge write recovery +
precharge time
Minimum time clocks remain ON after
CKE asynchronously drops LOW
DQ and DM input hold time
DQ and DM input pulse width for each
input
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew for DQS & associated
DQ signals
DQS latching rising transition to
associated clock edges
DQ and DM input setup time
DQS falling edge hold time from CK
DQS falling edge to CK setup time
Four Activate Window for 1KB page
size products
Four Activate Window for 2KB page
size products
CK half pulse width
Data-out high-impedance time from
CK / CK
Address and control input hold time
input reference level is the crosspoint when in differential strobe mode
t
RAS.MAX
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x
Component AC Timing Parameters
DRAM Component Timing Parameter by Speed Grade - DDR2–800 and DDR2–667
V
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
REF
CCD
CH.AVG
CK.AVG
CKE
CL.AVG
DAL
DELAY
DH.BASE
DIPW
DQSH
DQSL
DQSQ
DQSS
DS.BASE
DSH
DSS
FAW
FAW
HP
HZ
IH.BASE
V
stabilizes. During the period before
TT
.
DDR2–800
2
0.48
2500
3
0.48
WR +
t
+
125
0.35
0.35
0.35
—
– 0.25
50
0.2
0.2
35
45
Min(
t
—
250
Min.
IS
CL.ABS
t
+
IH
t
t
CH.ABS
CK .AVG
)
t
nRP
16
,
—
—
—
Max.
—
0.52
8000
—
0.52
—
––
––
200
+ 0.25
––
—
—
—
—
__
t
—
AC.MAX
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C
V
REF
DDR2–667
2
0.48
3000
3
0.48
WR +
t
t
175
0.35
0.35
0.35
—
– 0.25
100
0.2
0.2
37.5
50
Min(
t
—
275
Min.
IS
CK .AVG
CL.ABS
stabilizes, CKE = 0.2 x
+
t
CH.ABS
)
t
nRP
+
SO-DIMM DDR2 SDRAM Module
t
IH
,
Max.
—
0.52
8000
—
0.52
—
––
––
—
—
—
240
+ 0.25
––
—
—
—
—
__
t
—
AC.MAX
V
DDQ
Internet Data Sheet
Unit
nCK
t
ps
nCK
t
nCK
ns
ps
t
t
t
ps
t
ps
t
t
ns
ns
ps
ps
ps
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
TABLE 14
Note
)6)7)8)
10)11)
12)
10)11)
13)14)
15)19)20)
16)
17)
18)19)20)
17)
17)
35)
35)
21)
9)22)
23)25)
2)3)5
t
REFI
.