hys64t128020edl-3s-c2 Qimonda, hys64t128020edl-3s-c2 Datasheet - Page 17

• Manufacturer Part Number: hys64t128020edl-3s-c2
• Description: 200-pin So-dimm Ddr2 Sdram Modules So-dimm Sdram
• Manufacturer: Qimonda

1)
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
Rev. 1.00, 2008-07
12032007-B13H-E3X1
Parameter
DQ low impedance time from CK/CK
DQS/DQS low-impedance time from
CK / CK
MRS command to ODT update delay
Mode register set command cycle
time
OCD drive mode output delay
DQ/DQS output hold time from DQS
DQ hold skew factor
Average periodic refresh Interval
Auto-Refresh to Active/Auto-Refresh
command period
Read preamble
Read postamble
Active to active command period for
1KB page size products
Active to active command period for
2KB page size products
Internal Read to Precharge command
delay
Write preamble
Write postamble
Write recovery time
Internal write to read command delay
Exit active power down to read
command
Exit active power down to read
command (slow exit, lower power)
Exit precharge power-down to any
command
Exit self-refresh to a non-read
command
Exit self-refresh to read command
Write command to DQS associated
clock edges
V
and then restarted through the specified initialization sequence before normal operation can continue.
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
input reference level is the crosspoint when in differential strobe mode.
DDQ
= 1.8 V ± 0.1V;
V
DD
= 1.8 V ± 0.1 V.
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WL
LZ.DQ
LZ.DQS
MOD
MRD
OIT
QH
QHS
REFI
RFC
RPRE
RPST
RRD
RRD
RTP
WPRE
WPST
WR
WTR
XARD
XARDS
XP
XSNR
XSRD
DDR2–800
2 ×
t
0
2
0
t
—
—
—
127.5
0.9
0.4
7.5
10
7.5
0.35
0.4
15
7.5
2
8 – AL
2
t
200
RL – 1
Min.
AC.MIN
HP
RFC
–
t
+10
AC.MIN
t
QHS
17
Max.
t
t
12
—
12
—
300
7.8
3.9
—
1.1
0.6
—
—
—
—
0.6
—
—
—
—
—
—
—
AC.MAX
AC.MAX
HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2
DDR2–667
2 ×
t
0
2
0
t
—
—
—
127.5
0.9
0.4
7.5
10
7.5
0.35
0.4
15
7.5
2
7 – AL
2
t
200
RL–1
Min.
AC.MIN
HP
RFC
–
t
AC.MIN
+10
t
QHS
SO-DIMM DDR2 SDRAM Module
Max.
t
t
12
—
12
—
340
7.8
3.9
—
1.1
0.6
—
—
—
—
0.6
—
—
—
—
—
—
—
AC.MAX
AC.MAX
Internet Data Sheet
Unit
ps
ps
ns
nCK
ns
ps
ps
μs
μs
ns
t
t
ns
ns
ns
t
t
ns
ns
nCK
nCK
nCK
ns
nCK
nCK
CK.AVG
CK.AVG
CK.AVG
CK.AVG
Note
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8)21)
8)21)
34)
34)
25)
26)
27)28)
27)29)
30)
31)32)
31)33)
34)
34)
34)
34)
34)35)
34)
1)2)3