hys64t128020edl-3s-c2 Qimonda, hys64t128020edl-3s-c2 Datasheet - Page 4

• Manufacturer Part Number: hys64t128020edl-3s-c2
• Description: 200-pin So-dimm Ddr2 Sdram Modules So-dimm Sdram
• Manufacturer: Qimonda

1) This
2) Precharge-All command for an 8 bank device will equal to
1.2
The Qimonda HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2
module family are Small-Outline DIMM modules “SO-DIMMs”
with 30 mm height based on DDR2 technology. DIMMs are
available as non-ECC modules
256M × 64 (2GB) in organization and density, intended for
mounting into 200-pin connector sockets.
1) For detailed information regarding Product Type of Qimonda please see chapter "Product Type Nomenclature" of this data sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2–6400S–555–12–F0" where 6400S
Rev. 1.00, 2008-07
12032007-B13H-E3X1
Product Type
PC2-6400 (5-5-5)
HYS64T256020EDL-25FC2
HYS64T128020EDL-25FC2
PC2-6400 (6-6-6)
HYS64T256020EDL-2.5C2
HYS64T128020EDL-2.5C2
PC2-5300 (5-5-5)
HYS64T256020EDL-3S-C2
HYS64T128020EDL-3S-C2
where
means Small-Outline DIMM modules with 6.40 GB/sec Module Bandwidth and "555–12" means Column Address Strobe (CAS) latency
=5, Row Column Delay (RCD) latency = 5 and Row Precharge (RP) latency = 5 using the Industry Standard SPD Revision 1.2 and
produced on the Raw Card "F".
t
PREA
t
nRP
value is the minimum value at which this chip will be functional.
= RU{
1)
t
RP
Description
/
t
CK(avg)
} and
Compliance Code
2GB 2R×8 PC2–6400S–555–12–F0
1GB 2R×16 PC2–6400S–555–12–A0
2GB 2R×8 PC2–6400S–666–12–F0
1GB 2R×16 PC2–6400S–666–12–A0
2GB 2R×8 PC2–5300S–555–12–F0
1GB 2R×16 PC2–5300S–555–12–A0
t
RP
is the value for a single bank precharge.
in128M × 64 (1GB),
2)
t
RP
+ 1 ×
4
t
The memory array is designed with 1 Gbit Double-Data-
Rate-Two (DDR2) Synchronous DRAMs.
capacitors are mounted on the PCB board. The DIMMs
feature serial presence detect based on a serial E
device using the 2-pin I
programmed with configuration data and are write protected;
the second 128 bytes are available to the customer.
CK
or
t
nRP
+ 1 × nCK, depending on the speed bin,
HYS64T[128/256]020EDL–[25F/2.5/3S](–)C2
Description
2 Ranks, Non-ECC
2 Ranks, Non-ECC
2 Ranks, Non-ECC
2 Ranks, Non-ECC
2 Ranks, Non-ECC
2 Ranks, Non-ECC
SO-DIMM DDR2 SDRAM Module
2
C protocol. The first 128 bytes are
Ordering Information
SDRAM Technology
1Gbit (×8)
1Gbit (×16)
1Gbit (×8)
1Gbit (×16)
1Gbit (×8)
1Gbit (×16)
Internet Data Sheet
TABLE 2
Decoupling
2
PROM