hys64t128020edl Qimonda, hys64t128020edl Datasheet - Page 21

• Manufacturer Part Number: hys64t128020edl
• Description: 200-pin Small-outlined Ddr2 Sdram Modules
• Manufacturer: Qimonda

1) For details and notes see the relevant Qimonda component data sheet
2)
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
6) Inputs are not recognized as valid until
7) The output timing reference voltage level is
8) For each of the terms, if not already an integer, round to the next highest integer.
9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.
10) For timing definition, refer to the Component data sheet.
11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
Rev. 1.12, 2007-10
10312006-I253-V1V0
Parameter
OCD drive mode output delay
Data output hold time from DQS
Data hold skew factor
Average periodic refresh Interval
Average periodic refresh Interval
Auto-Refresh to Active/Auto-Refresh
command period
Precharge-All (8 banks) command period
Read preamble
Read postamble
Active bank A to Active bank B command
period
Internal Read to Precharge command
delay
Write preamble
Write postamble
Write recovery time for write without
Auto-Precharge
Internal Write to Read command delay
Exit power down to any valid command
(other than NOP or Deselect)
Exit active power-down mode to Read
command (slow exit, lower power)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit Self-Refresh to non-Read command
Exit Self-Refresh to Read command
Write recovery time for write with Auto-
Precharge
V
and then restarted through the specified initialization sequence before normal operation can continue.
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
input reference level is the crosspoint when in differential strobe mode. component
the WR parameter stored in the MR.
mis-match between DQS / DQS and associated DQ in any given cycle.
DDQ
= 1.8 V ± 0.1V;
V
DD
= 1.8 V ± 0.1 V.
V
REF
V
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WR
stabilizes. During the period before
OIT
QH
QHS
REFI
REFI
RFC
RP
RPRE
RPST
RRD
RTP
WPRE
WPST
WR
WTR
XARD
XARDS
XP
XSNR
XSRD
TT
. component datasheet
DDR2–533
0
t
—
—
—
127.5
t
0.9
0.40
7.5
0.25
0.40
15
7.5
2
6 – AL
2
t
200
t
Min.
HP
RP
10
RFC
WR
21
–
/
+ 1 ×
t
t
+10
CK
QHS
t
CK
V
t
REF
CK
Max.
12
—
400
7.8
3.9
—
—
—
—
—
—
—
—
—
—
—
—
1.1
0.60
0.60
refers to the application clock period. WR refers to
stabilizes, CKE = 0.2 x
Small Outlined DDR2 SDRAM Modules
HYS64T128020EDL–[2.5/3S/3.7]–B
Unit
ns
ps
µs
µs
ns
ns
t
t
ns
ns
t
t
ns
ns
t
t
t
ns
t
t
CK
CK
CK
CK
CK
CK
CK
CK
CK
V
DDQ
Internet Data Sheet
is recognized as low.
Notes
7)
14)15)
16)18)
17)
14)
14)
16)22)
19)
20)
21)
21)
22)
2)3)4)5)6)