hys64t128020eu-3s-b2 Qimonda, hys64t128020eu-3s-b2 Datasheet - Page 19

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hys64t128020eu-3s-b2

Manufacturer Part Number
hys64t128020eu-3s-b2
Description
240-pin Unbuffered Ddr2 Sdram Modules Udimm Sdram
Manufacturer
Qimonda
Datasheet
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
3) Inputs are not recognized as valid until
4) The output timing reference voltage level is
5)
6) For products released before 01-09-2007.
7) Products released after 01-09-2007 can support
Rev. 1.01, 2008-01
10202006-L0SM-FEYT
Speed Grade
QAG Sort Name
CAS-RCD-RP latencies
t
Parameter
Clock Period
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
CK
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
input reference level is the crosspoint when in differential strobe mode.
t
RAS.MAX
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x
@ CL = 3
@ CL = 4
@ CL = 5
Symbol
t
t
t
t
t
t
t
CK
CK
CK
RAS
RC
RCD
RP
V
REF
V
stabilizes. During the period before
TT
DDR2–667C
–3
4–4–4
Min.
5
3
3
40
57
12
12
.
t
RAS.MIN
= 40 ns for all DDR2 speed sort.
Max.
8
8
8
70k
19
DDR2–667D
5–5–5
Min.
5
3.75
3
40
60
15
15
–3S
HYS[64/72]T[32/64/128]xxxEU-[25F/2.5/3/3S/3.7]-B2
Max.
8
8
8
70k
V
REF
stabilizes, CKE = 0.2 x
DDR2–533C
–3.7
4–4–4
Min.
5
3.75
3.75
40
60
15
15
Unbuffered DDR2 SDRAM Module
Max.
8
8
8
70k
Speed Grade Definition
V
DDQ
Internet Data Sheet
Unit
ns
ns
ns
ns
ns
ns
ns
TABLE 13
Note
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)7)
1)2)3)4)
1)2)3)4)
1)2)3)4)
t
REFI
.

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