hys64t128020eu-3s-b2 Qimonda, hys64t128020eu-3s-b2 Datasheet - Page 8

• Manufacturer Part Number: hys64t128020eu-3s-b2
• Description: 240-pin Unbuffered Ddr2 Sdram Modules Udimm Sdram
• Manufacturer: Qimonda

Rev. 1.01, 2008-01
10202006-L0SM-FEYT
Ball No.
73
Address Signals
71
190
54
188
183
63
182
61
60
180
58
179
177
70
57
176
196
174
Data Signals
3
4
9
10
122
123
128
129
Name
WE
BA0
BA1
BA2
NC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
A13
NC
A14
NC
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Pin
Type
I
I
I
I
NC
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
NC
I
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Buffer
Type
SSTL
SSTL
SSTL
SSTL
—
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
—
SSTL
—
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Function
Write Enable
Bank Address Bus 1:0
Selects which DDR2 SDRAM internal bank of four or eight is activated.
Bank Address Bus 2
Greater than 512Mb DDR2 SDRAMS
Not Connected
Less than 1Gb DDR2 SDRAMS
Address Bus 12:0
During a Bank Activate command cycle, defines the row address when
sampled at the crosspoint of the rising edge of CK and falling edge of CK.
During a Read or Write command cycle, defines the column address when
sampled at the cross point of the rising edge of CK and falling edge of CK. In
addition to the column address, AP is used to invoke autoprecharge operation
at the end of the burst read or write cycle. If AP is HIGH, autoprecharge is
selected and BA0-BAn defines the bank to be precharged. If AP is LOW,
autoprecharge is disabled. During a Precharge command cycle, AP is used
in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is
HIGH, all banks will be precharged regardless of the state of BA0-BAn inputs.
If AP is LOW, then BA0-BAn are used to define which bank to precharge.
Address Signal 13
Note: 1 Gbit based module and 512M
Not Connected
Note: Module based on 1 Gbit
Address Signal 14
Note: Modules based on 2 Gbit
Not Connected
Note: Modules based on 1 Gbit or smaller
Data Bus 63:0
Data Input / Output pins
8
HYS[64/72]T[32/64/128]xxxEU-[25F/2.5/3/3S/3.7]-B2
×
16Module based on 512 Mbit
Unbuffered DDR2 SDRAM Module
×4/×8
Internet Data Sheet
×
16 or smaller