hys64t128020emv-2.5c2 Qimonda, hys64t128020emv-2.5c2 Datasheet - Page 4

• Manufacturer Part Number: hys64t128020emv-2.5c2
• Description: 214-pin 1.5v Unbuffered Ddr2 Sdram Microdimm Modules Mdimm Sdram
• Manufacturer: Qimonda

1) This
2) Precharge-All command for an 8 bank device will equal to
1.2
The Qimonda HYS64T128020EMV–[2.5/3S](–)C2 module
family are Micro-DIMM modules “MDIMMs” with 30 mm
height based on DDR2 technology. DIMMs are available as
non-ECC modules in128M × 64 (1GB) in organization and
density, intended for mounting into 214-pin connector
sockets.
1) For detailed information regarding Product Type of Qimonda please see chapter "Product Type Nomenclature" of this data sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2–6400M–666–12–A0" where
Rev. 1.00, 2008-06
01242008-CDK4-KSK6
QAG Speed Code
DRAM Speed Grade
Module Speed Grade
CAS-RCD-RP latencies
Min. Row Cycle Time
Precharge-All (8 banks) command period
Product Type
PC2-6400 (6-6-6)
HYS64T128020EMV-2.5C2
PC2-5300 (5-5-5)
HYS64T128020EMV-3S-C2
DIMM
Density
1GB
where
6400M means Micro-DIMM modules with 6.40 GB/sec Module Bandwidth and "666–12" means Column Address Strobe (CAS) latency
=6, Row Column Delay (RCD) latency = 6 and Row Precharge (RP) latency = 6 using the Industry Standard SPD Revision 1.2 and
produced on the Raw Card "A".
t
PREA
t
nRP
value is the minimum value at which this chip will be functional.
= RU{
1)
Module
Organization
128M × 64
t
RP
Description
/
t
CK(avg)
} and
Compliance Code
1GB 2R×16 PC2–6400M–666–12–A0
1GB 2R×16 PC2–5300M–555–12–A0
t
RP
is the value for a single bank precharge.
Memory
Ranks
2
DDR2
PC2
t
t
RC
PREA
2)
t
RP
ECC/
Non-ECC
Non-ECC
+ 1 ×
4
t
–2.5
–800E
–6400E
6–6–6
60
17.5
The memory array is designed with 1 Gbit Double-Data-
Rate-Two (DDR2) Synchronous DRAMs.
capacitors are mounted on the PCB board. The DIMMs
feature serial presence detect based on a serial E
device using the 2-pin I
programmed with configuration data and are write protected;
the second 128 bytes are available to the customer.
CK
or
t
nRP
Unbuffered DDR2 SDRAM MicroDIMM Modules
# of SDRAMs # of row/bank/column
8
+ 1 × nCK, depending on the speed bin,
Description
2 Ranks, Non-ECC
2 Ranks, Non-ECC
–3S
–667D
–5300D
5–5–5
60
18
HYS64T128020EMV–[2.5/3S](–)C2
bits
13/3/10
2
C protocol. The first 128 bytes are
Unit
t
ns
ns
CK
Ordering Information
SDRAM Technology
1Gbit (×16)
1Gbit (×16)
Internet Data Sheet
Address Format
TABLE 2
TABLE 3
Note
1)2)
Decoupling
Raw
Card
A
2
PROM