hys64t128020emv-2.5c2 Qimonda, hys64t128020emv-2.5c2 Datasheet - Page 6

• Manufacturer Part Number: hys64t128020emv-2.5c2
• Description: 214-pin 1.5v Unbuffered Ddr2 Sdram Microdimm Modules Mdimm Sdram
• Manufacturer: Qimonda

2
2.1
The pin configuration of the DDR2 SDRAM Micro-DIMM is listed by function in
columns Pin and Buffer Type are explained in
Rev. 1.00, 2008-06
01242008-CDK4-KSK6
Ball No.
Clock Signals
122
194
123
195
43
147
Control Signals
165
62
Name
CK0
CK1
CK0
CK1
CKE0
CKE1
NC
S0
S1
NC
Pin Configurations
Pin Configurations
Pin
Type
I
I
I
I
I
I
NC
I
I
NC
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Table 6
Function
Clock Signal CK 1:0, Complementary Clock Signal CK 1:0
Note: The system clock inputs. All address and command lines are
Clock Enables 1:0
Notes:
1. Activates the DDR2 SDRAM CK signal when HIGH and deactivates
2. 2-rank module
Not Connected
Note: 1-rank module
Chip Select Rank 1:0
Notes:
1. Enables the associated DDR2 SDRAM command decoder when LOW
2. 2-rank module
Not Connected
Note: 1-rank module
and
the CK signal when LOW. By deactivating the clocks, CKE0 initiates
the Power Down Mode or the Self Refresh Mode.
and disables the command decoder when HIGH. When the command
decoder is disabled, new commands are ignored but previous
operations continue. Rank 0 is selected by S0; Rank 1 is selected by
S1.
sampled on the cross point of the rising edge of CK and the falling
edge of CK. A Delay Locked Loop (DLL) circuit is driven from the
clock inputs and output timing for read operations is synchronized
to the input clock.
Table 7
6
respectively. The pin numbering is depicted in
Unbuffered DDR2 SDRAM MicroDIMM Modules
Table 5
HYS64T128020EMV–[2.5/3S](–)C2
(214 pins). The abbreviations used in
Pin Configuration of MDIMM
Internet Data Sheet
TABLE 5
Figure
1.