hys64t128020emv-2.5c2 Qimonda, hys64t128020emv-2.5c2 Datasheet - Page 7

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hys64t128020emv-2.5c2

Manufacturer Part Number
hys64t128020emv-2.5c2
Description
214-pin 1.5v Unbuffered Ddr2 Sdram Microdimm Modules Mdimm Sdram
Manufacturer
Qimonda
Datasheet
Rev. 1.00, 2008-06
01242008-CDK4-KSK6
Ball No.
163
60
56
Address Signals
55
162
46
161
159
52
158
51
50
157
48
155
154
54
47
153
167
Data Signals
3
4
9
10
109
110
114
115
12
13
Name
RAS
CAS
WE
BA0
BA1
BA2
NC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
A13
NC
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
Pin
Type
I
I
I
I
I
I
NC
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Function
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
Note: When sampled at the cross point of the rising edge of CK,and
Bank Address Bus 1:0
Note: Select internal SDRAM memory bank
Bank Address Bus 2
Note: Greater than 512Mb DDR2 SDRAMS
Not Connected
Note: Less than 1Gb DDR2 SDRAMS
Address Inputs 12:0, Address Input 10/Autoprecharge
Note: During a Bank Activate command cycle, defines the row address
Address Input 13
Note: Modules based on
Not Connected
Note: Modules based on
Data Bus 63:0
Note: Data Input / Output pins
falling edge of CK, RAS, CAS and WE define the operation to be
executed by the SDRAM.
when sampled at the crosspoint of the rising edge of CK and falling
edge of CK. During a Read or Write command cycle, defines the
column address when sampled at the cross point of the rising edge
of CK and falling edge of CK. In addition to the column address, AP
is used to invoke autoprecharge operation at the end of the burst
read or write cycle. If AP is HIGH, autoprecharge is selected and
BA[2:0] defines the bank to be precharged. If AP is LOW,
autoprecharge is disabled. During a Precharge command cycle, AP
is used in conjunction with BA[2:0] to control which bank(s) to
precharge. If AP is HIGH, all banks will be precharged regardless
of the state of BA[2:0] inputs. If AP is LOW, then BA[2:0] are used
to define which bank to precharge.
7
Unbuffered DDR2 SDRAM MicroDIMM Modules
×
×
4/
16 component
×
8 component
HYS64T128020EMV–[2.5/3S](–)C2
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