hys64t128020emv-2.5c2 Qimonda, hys64t128020emv-2.5c2 Datasheet - Page 9

• Manufacturer Part Number: hys64t128020emv-2.5c2
• Description: 214-pin 1.5v Unbuffered Ddr2 Sdram Microdimm Modules Mdimm Sdram
• Manufacturer: Qimonda

Rev. 1.00, 2008-06
01242008-CDK4-KSK6
Ball No.
92
93
191
192
200
201
95
96
101
102
203
204
208
209
7
6
19
18
28
27
140
139
71
70
186
185
198
197
99
98
112
120
131
36
177
79
90
206
EEPROM
Name
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS0
DQS0
DQS1
DQS1
DQS2
DQS2
DQS3
DQS3
DQS4
DQS4
DQS5
DQS5
DQS6
DQS6
DQS7
DQS7
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
Pin
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Function
Data Bus 63:0
Note: Data Input / Output pins
Data Strobe Bus 7:0 and Complementary Data Strobe Bus 7:0
Notes:
1. The data strobes, associated with one data byte, sourced with data
2. See block diagram for corresponding DQ signals
Data Masks 7:0
Note: The data write masks, associated with one data byte. In Write
transfers. In Write mode, the data strobe is sourced by the controller
and is centered in the data window. In Read mode the data strobe is
sourced by the DDR2 SDRAM and is sent at the leading edge of the
data window. DQS signals are complements, and timing is relative to
the crosspoint of respective DQS and DQS. If the module is to be
operated in single ended strobe mode, all DQS signals must be tied
on the system board to
programmed appropriately.
mode, DM operates as a byte mask by allowing input data to be
written if it is LOW but blocks the write operation if it is HIGH. In
Read mode, DM lines have no effect.
9
Unbuffered DDR2 SDRAM MicroDIMM Modules
V
SS
and DDR2 SDRAM mode registers
HYS64T128020EMV–[2.5/3S](–)C2
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