hys64t128020hm-5-a Infineon Technologies Corporation, hys64t128020hm-5-a Datasheet - Page 20

• Manufacturer Part Number: hys64t128020hm-5-a
• Description: 214-pin Micro-dimm-ddr2-sdram Modules
• Manufacturer: Infineon Technologies Corporation

Table 12
Parameter
Exit precharge power-down to any
valid command (other than NOP or
Deselect)
Exit Self-Refresh to non-Read
command
Exit Self-Refresh to Read
command
1) For details and notes see the relevant INFINEON component data sheet
2) VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1 V. See notes
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross.
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is
7) The output timing reference voltage level is VTT. See Chapter 8 for the reference load for timing measurements.
8)
9) 8 bank device Sequential Activation Restriction. No more than 4 banks may be activated in a rolling
10) 16 (2k page size), not on 256 Mbit component
Table 13
Symbol
CK0, CK0
CKE0-
CKEn
RAS, CAS,
WE
BA0-BAn
Data Sheet
S0-Sn
powered down and then restarted through the specified initialization sequence before normal operation can continue.
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other
Slew Rates see Chapter 8 of this data sheet. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1
= 0) under the Reference Load for Timing Measurements according to Chapter 8.1 only.
The DQS / DQS, RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode;
The input reference level for signals other than CK/CK, DQS / DQS, RDQS / RDQS is defined in Chapter 8.3 of this data
sheet.
recognized as low.
4 & 8 (1k page size)
Timing Parameter by Speed Grade - DDR2-400 & DDR2-533 (cont’d)
Input/Output Functional Description
I
I
I
I
Type
I
Polarity Function
Cross
point
Active
High
Active
Low
Active
Low
—
The system clock inputs. All address and command lines are sampled on the
cross point of the rising edge of CK and the falling edge of CK. A Delay Locked
Loop (DLL) circuit is driven from the clock inputs and output timing for read
operations is synchronized to the input clock.
Activates the DDR2 SDRAM CK signal when 1 and deactivates the CK signal
when 0. By deactivating the clocks, CKE 0 initiates the Power Down Mode or the
Self Refresh Mode.
Enables the associated DDR2 SDRAM command decoder when 0 and disables
the command decoder when 1. When the command decoder is disabled, new
commands are ignored but previous operations continue. Rank 0 is selected by
S0; Rank 1 is selected by S1. The input signals also disable all outputs (except
CKE and ODT) of the register(s) on the DIMM when both inputs are high. When
S is high, all register outputs (except CK, ODT and Chip select) remain in the
previous state.
When sampled at the cross point of the rising edge of CK,and falling edge of CK,
RAS, CAS and WE define the operation to be executed by the SDRAM.
Selects internal SDRAM memory bank
Symbol
t
t
t
XP
XSNR
XSRD
DDR2–533
Min.
2
t
200
RFC
3)4)5)6)
+10
20
Max.
—
—
—
Micro-DIMM DDR2 SDRAM Modules
DDR2–400
Min.
2
t
200
RFC
HYS64T128020HM–[3.7/5]–A
+10
Electrical Characteristics
Max.
—
—
—
04132004-S0LP-CL4Q
t
FAW
Rev. 1.2, 2005-08
window.
Unit Note
t
ns
t
CK
CK
2)3)4)5)6)
7)
1)