gs881z36bgd-250v GSI Technology, gs881z36bgd-250v Datasheet

no-image

gs881z36bgd-250v

Manufacturer Part Number
gs881z36bgd-250v
Description
9mb Pipelined And Flow Through Synchronous Nbt Sram
Manufacturer
GSI Technology
Datasheet
100-Pin TQFP & 165-Bump BGA
Commercial Temp
Industrial Temp
Features
• User-configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
• Fully pin-compatible with both pipelined and flow through
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 1.8 V or 2.5 V core power supply
• 1.8 V or 2.5 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 18M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ pin for automatic power-down
• JEDEC-standard packages
• RoHS-compliant 100-lead TQFP and 165-bump BGA
Functional Description
The GS881Z18/32/36B(T/D)-xxxV is a 9Mbit Synchronous
Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL
or other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Rev: 1.01 4/2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
read-write-read bus utilization
NtRAM™, NoBL™ and ZBT™ SRAMs
packages available
Flow Through
Pipeline
3-1-1-1
2-1-1-1
9Mb Pipelined and Flow Through
Curr (x32/x36)
Curr (x32/x36)
Synchronous NBT SRAM
Curr (x18)
Curr (x18)
tCycle
tCycle
t
t
KQ
KQ
Paramter Synopsis
1/37
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable, ZZ and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS881Z18/32/36B(T/D)-xxxV may be configured by the
user to operate in Pipeline or Flow Through mode. Operating
as a pipelined synchronous device, in addition to the rising-
edge-triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS881Z18/32/36B(T/D)-xxxV is implemented with GSI's
high performance CMOS technology and is available in
JEDEC-standard 100-pin TQFP and 165-bump BGA packages.
-250
200
230
160
185
3.0
4.0
5.5
5.5
-200
170
195
140
160
3.0
5.0
6.5
6.5
-150
140
160
128
145
3.8
6.7
7.5
7.5
GS881Z18/32/36B(T/D)-xxxV
Unit
mA
mA
mA
mA
ns
ns
ns
ns
© 2006, GSI Technology
250 MHz–150 MHz
1.8 V or 2.5 V V
1.8 V or 2.5 V I/O
DD

Related parts for gs881z36bgd-250v

gs881z36bgd-250v Summary of contents

Page 1

... Curr (x18) 200 170 Curr (x32/x36) 230 195 t 5.5 6.5 KQ 5.5 6.5 tCycle Curr (x18) 160 140 Curr (x32/x36) 185 160 1/37 GS881Z18/32/36B(T/D)-xxxV 250 MHz–150 MHz 2.5 V I/O -150 Unit 3.8 ns 6.7 ns 140 mA 160 mA 7.5 ns 7.5 ns 128 mA 145 mA © 2006, GSI Technology DD ...

Page 2

... DDQ DQP DDQ DDQ DDQ © 2006, GSI Technology ...

Page 3

... DDQ DDQ DDQ © 2006, GSI Technology ...

Page 4

... DDQ DDQ DDQ DQP 51 A © 2006, GSI Technology ...

Page 5

... Linear Burst Order; active low. Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Core power supply Ground Output driver power supply 5/37 GS881Z18/32/36B(T/D)-xxxV ; active low A ; active low B ; active low C ; active low D © 2006, GSI Technology ...

Page 6

... DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ © 2006, GSI Technology ...

Page 7

... DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ © 2006, GSI Technology ...

Page 8

... DDQ DDQ DDQ DDQ DDQ DDQ DDQ V NC DQP N A DDQ © 2006, GSI Technology ...

Page 9

... Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Must Connect High Do Not Use Core power supply I/O and Core Ground Output driver power supply 9/37 © 2006, GSI Technology ...

Page 10

... GS881Z18/32/36B(T/D)-xxxV NBT SRAM Functional Block Diagram Rev: 1.01 4/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS881Z18/32/36B(T/D)-xxxV Amps Sense Drivers Write 10/37 © 2006, GSI Technology ...

Page 11

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com & determine which bytes will be written. All or none may be activated. A write cycle D 11/37 GS881Z18/32/36B(T/D)-xxxV , E and E ). Deassertion of any one of the Enable © 2006, GSI Technology ...

Page 12

... High-Z 1,2,3, High High High High High High © 2006, GSI Technology Notes 1,10 2 1,2,10 3 1,3, ...

Page 13

... and D represent input command codes as indicated in the Synchronous Truth Table. n+1 n+2 ƒ ƒ Next State Pipelined and Flow Through Read/Write Control State Diagram 13/37 GS881Z18/32/36B(T/D)-xxxV New Write Burst Write B D n+3 ƒ ƒ © 2006, GSI Technology ...

Page 14

... and D represent input command codes as indicated in the Truth Tables. Next State (n+2) n n+1 n+2 ƒ ƒ Intermediate Current State State Pipeline Mode Data I/O State Diagram 14/37 GS881Z18/32/36B(T/D)-xxxV Intermediate R B Data Out W (Q Valid) D n+3 ƒ ƒ Next State © 2006, GSI Technology ...

Page 15

... Pipeline and Flow through Read Write Control State Diagram 15/37 GS881Z18/32/36B(T/D)-xxxV R B Data Out W (Q Valid) D Notes: 1. The Hold command (CKE Low) is not shown because it prevents any state change and D represent input command codes as indicated in the Truth Tables. n+2 n+3 ƒ ƒ © 2006, GSI Technology ...

Page 16

... Note: The burst counter wraps to initial state on the 5th clock. 16/37 GS881Z18/32/36B(T/D)-xxxV Function Linear Burst Interleaved Burst Flow Through Pipeline Active Standby A[1:0] A[1:0] A[1:0] A[1: BPR 1999.05.18 © 2006, GSI Technology ...

Page 17

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Sleep Mode Timing Diagram tKH tKH tKL tKL tZZS tZZH 17/37 GS881Z18/32/36B(T/D)-xxxV 2. The duration of SB tZZR on pipelined parts and V on flow DDQ SS © 2006, GSI Technology ...

Page 18

... DDn 18/37 GS881Z18/32/36B(T/D)-xxxV Value –0.5 to 4.6 –0 –0 +0.5 (≤ 4.6 V max.) DDQ –0 +0.5 (≤ 4.6 V max.) DD +/–20 +/–20 1.5 –55 to 125 –55 to 125 Typ. Max. Unit 1.8 2.0 V 2 © 2006, GSI Technology Unit Notes ...

Page 19

... Symbol Test conditions I/O OUT 19/37 GS881Z18/32/36B(T/D)-xxxV Typ. Max. Unit V + 0.3 V — DD 0.3*V V — DD Typ. Max. Unit ° ° 20% tKC DD IL Typ. Max. Unit © 2006, GSI Technology Notes 1 1 Notes 2 2 ...

Page 20

... Figure 1 Output Load 1 * 50Ω 30pF V DDQ/2 * Distributed Test Jig Capacitance Min – ≥ –100 –1 uA OUT DD Min = 1 – 0.4 V DDQ DDQ = 2.375 V 1.7 V — — © 2006, GSI Technology Max 1 uA 100 Max — — 0.4 V 0.4 V ...

Page 21

... GSI Technology Unit ...

Page 22

... GSI Technology ...

Page 23

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Pipeline Mode Timing (NBT) Suspend Read C Write D writeno-op tKH tKH tKC tKC tKL tKL D(A) Q(B) Q(C) 23/37 GS881Z18/32/36B(T/D)-xxxV Read E Deselect E tLZ tHZ tKQ tKQX D(D) Q(E) © 2006, GSI Technology ...

Page 24

... Write B+1 Read C Cont tKL tKL tKH tKH tKC tKC C D tKQ tLZ D(B) D(B+1) Q(C) tOHZ 24/37 GS881Z18/32/36B(T/D)-xxxV Read D Write E Read F Write tKQ tKQX tHZ tLZ Q(D) D(E) Q(F) tOLZ tOE . The JTAG output DD . TDO should be left unconnected. SS © 2006, GSI Technology tKQX D(G) ...

Page 25

... Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. Rev: 1.01 4/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS881Z18/32/36B(T/D)-xxxV Description 25/37 © 2006, GSI Technology ...

Page 26

... Control Signals Test Access Port (TAP) Controller Not Used 26/37 GS881Z18/32/36B(T/D)-xxxV · · · TDO GSI Technology JEDEC Vendor ID Code © 2006, GSI Technology 0 1 ...

Page 27

... JTAG Tap Controller State Diagram 1 1 Select Capture DR 0 Shift Exit1 DR 0 Pause Exit2 Update 27/37 GS881Z18/32/36B(T/D)-xxxV 1 Select Capture IR 0 Shift Exit1 IR 0 Pause Exit2 Update © 2006, GSI Technology ...

Page 28

... Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. Rev: 1.01 4/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS881Z18/32/36B(T/D)-xxxV 28/37 © 2006, GSI Technology ...

Page 29

... Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 1.01 4/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS881Z18/32/36B(T/D)-xxxV Description 29/37 Notes © 2006, GSI Technology ...

Page 30

... DD2 DD2 –300 1 uA 100 uA –1 – 1.7 V — 0.4 V — – 100 mV — V DDQ 100 mV V — JTAG Port AC Test Load DQ 50Ω 30pF V /2 DDQ * Distributed Test Jig Capacitance © 2006, GSI Technology ...

Page 31

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. tTKC tTKC tTKH tTKH tTH tTS tTH tTS tTKQ tTH tTS Min Max Unit — — — — ns — — ns 31/37 GS881Z18/32/36B(T/D)-xxxV tTKL tTKL © 2006, GSI Technology ...

Page 32

... All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. Rev: 1.01 4/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. θ 0.10 0.15 1.40 1.45 0.30 0.40 — 0.20 e 22.0 22.1 20.0 20.1 16.0 16.1 b 14.0 14.1 0.65 — 0.60 0.75 1.00 — 0.10 — 7° 32/37 GS881Z18/32/36B(T/D)-xxxV E1 E © 2006, GSI Technology ...

Page 33

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS881Z18/32/36B(T/D)-xxxV BOTTOM VIEW Ø0. Ø0. Ø0.40~0.60 (165x 1.0 10.0 13±0.05 B 0.20(4x) 33/37 A1 CORNER 1.0 © 2006, GSI Technology ...

Page 34

... GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings Rev: 1.01 4/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ...

Page 35

... GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings Rev: 1.01 4/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ...

Page 36

... Ordering Information—GSI NBT Synchronous SRAM 1 Org Part Number 256K x 36 GS881Z36BGD-250V 256K x 36 GS881Z36BGD-200V 256K x 36 GS881Z36BGD-150V 512K x 18 GS881Z18BGD-250IV 512K x 18 GS881Z18BGD-200IV 512K x 18 GS881Z18BGD-150IV 256K x 32 GS881Z32BGD-250IV 256K x 32 GS881Z32BGD-200IV 256K x 32 GS881Z32BGD-150IV 256K x 36 GS881Z36BGD-250IV 256K x 36 ...

Page 37

... Rev: 1.01 4/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Page;Revisions;Reason • Creation of new datasheet • Removed parity references (pg. 1, 16, 17) Content • Added note to TQFP pinouts (pg 37/37 GS881Z18/32/36B(T/D)-xxxV © 2006, GSI Technology ...

Related keywords