gs88136bgt-333i GSI Technology, gs88136bgt-333i Datasheet

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gs88136bgt-333i

Manufacturer Part Number
gs88136bgt-333i
Description
512k X 18, 256k X 32, 256k X 36 9mb Sync Burst Srams
Manufacturer
GSI Technology
Datasheet
100-pin TQFP & 165-bump BGA
Commercial Temp
Industrial Temp
Features
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP and 165-bump BGA
• RoHS-compliant 100-lead TQFP and 165-bump BGA
Functional Description
Applications
The GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D) is a
9,437,184-bit high performance synchronous SRAM with a 2-
bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1, E2), address burst
control inputs (ADSP, ADSC, ADV) and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Rev: 1.06 6/2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
packages
packages available
Flow Through
Pipeline
3-1-1-1
2-1-1-1
Curr (x32/x36)
Curr (x32/x36)
512K x 18, 256K x 32, 256K x 36
Curr (x18)
Curr (x18)
tCycle
tCycle
t
t
KQ
KQ
9Mb Sync Burst SRAMs
Paramter Synopsis
1/38
-333
250
290
200
230
2.5
3.0
4.5
4.5
GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)
-300
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
SCD Pipelined Reads
The GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D) is a
SCD (Single Cycle Deselect) pipelined synchronous SRAM.
DCD (Dual Cycle Deselect) versions are also available. SCD
SRAMs pipeline deselect commands one stage less than read
commands. SCD RAMs begin turning off their outputs
immediately after the deselect command has been captured in
the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)
operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V
and 2.5 V compatible. Separate output power (V
used to decouple output noise from the internal circuits and are
3.3 V and 2.5 V compatible.
230
265
185
210
2.5
3.3
5.0
5.0
-250
200
230
160
185
2.5
4.0
5.5
5.5
-200
170
195
140
160
3.0
5.0
6.5
6.5
-150
140
160
128
145
3.8
6.7
7.5
7.5
Unit
mA
mA
mA
mA
ns
ns
ns
ns
© 2002, GSI Technology
333 MHz–150 MHz
2.5 V or 3.3 V V
2.5 V or 3.3 V I/O
DDQ
) pins are
DD

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gs88136bgt-333i Summary of contents

Page 1

... KQ 4.5 5.0 5.5 tCycle Curr (x18) 200 185 160 Curr (x32/x36) 230 210 185 1/38 333 MHz–150 MHz 3.3 V I/O ) pins are DDQ -200 -150 Unit 3.0 3.8 ns 5.0 6.7 ns 170 140 mA 195 160 mA 6.5 7.5 ns 6.5 7.5 ns 140 128 mA 160 145 mA © 2002, GSI Technology DD ...

Page 2

... DDQ DQP DDQ DDQ DDQ © 2002, GSI Technology ...

Page 3

... DDQ DDQ DDQ © 2002, GSI Technology ...

Page 4

... DDQ DDQ DDQ DQP 51 A © 2002, GSI Technology ...

Page 5

... Sleep Mode control; active high Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Core power supply I/O and Core Ground Output driver power supply 5/38 © 2002, GSI Technology ...

Page 6

... DQA C DDQ V NC DQA D DDQ V NC DQA E DDQ V NC DQA F DDQ V NC DQA G DDQ DQA NC J DDQ V DQA NC K DDQ V DQA NC L DDQ V DQA NC M DDQ DDQ © 2002, GSI Technology ...

Page 7

... DDQ V DQB DQB D DDQ V DQB DQB E DDQ V DQB DQB F DDQ V DQB DQB G DDQ DQA DQA J DDQ V DQA DQA K DDQ V DQA DQA L DDQ V DQA DQA M DDQ DDQ © 2002, GSI Technology ...

Page 8

... DQPB C DDQ V DQB DQB D DDQ V DQB DQB E DDQ V DQB DQB F DDQ V DQB DQB G DDQ DQA DQA J DDQ V DQA DQA K DDQ V DQA DQA L DDQ V DQA DQA M DDQ V NC DQPA N DDQ © 2002, GSI Technology ...

Page 9

... Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Must Connect Low Core power supply I/O and Core Ground Output driver power supply 9/38 I/Os; active low D © 2002, GSI Technology ...

Page 10

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/ Counter Load Register D Q Register D Q Register D Q Register D Q Register D Q Register D Q Register 10/38 A Memory Array – DQx1 DQx9 © 2002, GSI Technology ...

Page 11

... may be used in any combination with BW to write single or multiple bytes. D 11/ Notes and/ © 2002, GSI Technology ...

Page 12

... High High High High © 2002, GSI Technology ...

Page 13

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D) Simplified State Diagram X Deselect First Write Burst Write CR CW 13/ First Read Burst Read BW, and GW) control inputs, and © 2002, GSI Technology ...

Page 14

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D) Simplified State Diagram with G X Deselect First Write Burst Write 14/ First Read Burst Read CR © 2002, GSI Technology ...

Page 15

... V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn 15/38 Value –0.5 to 4.6 –0.5 to 4.6 –0 +0.5 (≤ 4.6 V max.) DDQ –0 +0.5 (≤ 4.6 V max.) DD +/–20 +/–20 1.5 –55 to 125 –55 to 125 Typ. Max. Unit 3.3 3.6 V 2.5 2.7 V 3.3 3.6 V 2.5 2.7 V © 2002, GSI Technology Unit Notes ...

Page 16

... not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn 16/38 Max. Unit Notes 0.3 V 1,3 DDQ 0.8 V 1,3 Max. Unit Notes 0.3 0.3 V 1,3 DDQ 0.3*V V 1,3 DD Max. Unit Notes ° ° © 2002, GSI Technology ...

Page 17

... DD 50 Symbol Test conditions I/O OUT Conditions V – DDQ Fig. 1 Output Load 1 DQ 50Ω V DDQ/2 * Distributed Test Jig Capacitance 17/38 50% tKC DD IL Typ. Max. Unit 30pF © 2002, GSI Technology ...

Page 18

... –8 mA, V OH2 OH DDQ –8 mA, V OH3 OH DDQ 18/38 Min – ≥ V – ≤ V –1 uA 100 – 2.375 V 1 3.135 V 2.4 V — © 2002, GSI Technology Max — — 0.4 V ...

Page 19

... GSI Technology -150 –40 Unit to 85°C 160 mA 20 150 mA 15 150 mA 10 140 ...

Page 20

... GSI Technology Unit ...

Page 21

... ADSC initiated read and E3 only sampled with ADSP and ADSC tS tOHZ tH Q(A) D(B) 21/38 Read C+1 Read C+2 Read C+3 Cont Burst Read Burst Read Deselected with E1 E1 masks ADSP tKQ tLZ Q(C) Q(C+1) Q(C+2) Q(C+3) © 2002, GSI Technology Deselect tKQX tHZ ...

Page 22

... GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D) Flow Through Mode Timing Cont Write B Read C Read C+1 Read C+2 Read C+3 Read C tKL tKL tKC tKC Fixed High tS tH ADSC initiated read tKQ tOHZ tLZ D(B) Q(C) 22/38 Cont Deselect Deselected with E1 tHZ Q(C+1) Q(C+2) Q(C+3) Q(C) © 2002, GSI Technology tKQX ...

Page 23

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D) Sleep Mode Timing Diagram tKH tKH tKC tKC tKL tKL tZZS tZZH 23/38 2. The duration of SB tZZR . The JTAG output DD . TDO should be left unconnected. SS © 2002, GSI Technology ...

Page 24

... Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. Rev: 1.06 6/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D) Description 24/38 © 2002, GSI Technology ...

Page 25

... JTAG TAP Block Diagram · · · · · · Boundary Scan Register 0 Bypass Register Instruction Register ID Code Register · · · · Control Signals Test Access Port (TAP) Controller 25/38 · · TDO © 2002, GSI Technology ...

Page 26

... 26/38 GSI Technology I/O JEDEC Vendor ID Code © 2002, GSI Technology ...

Page 27

... JTAG Tap Controller State Diagram 1 1 Select Capture DR 0 Shift Exit1 DR 0 Pause Exit2 Update 27/38 1 Select Capture IR 0 Shift Exit1 IR 0 Pause Exit2 Update © 2002, GSI Technology ...

Page 28

... Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. Rev: 1.06 6/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D) 28/38 © 2002, GSI Technology ...

Page 29

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D) Conditions V – DDQ V /2 DDQ Description 29/38 JTAG Port AC Test Load 50Ω * 30pF V /2 DDQ * Distributed Test Jig Capacitance Notes © 2002, GSI Technology ...

Page 30

... Unit Notes V +0.3 2.0 V DD3 –0.3 0 +0.3 V DD2 DD2 0 –0.3 V DD2 1 uA –300 –1 100 –1 1.7 — V 0.4 V — V – 100 mV V — DDQ — 100 mV V tTKL tTKL © 2002, GSI Technology ...

Page 31

... For information regarding the Boundary Scan Chain obtain BSDL files for this part, please contact our Applications Engineering Department at: apps@gsitechnology.com. Rev: 1.06 6/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D) Min Max Unit 50 — ns — — — ns — — ns 31/38 © 2002, GSI Technology ...

Page 32

... All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. Rev: 1.06 6/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D) θ 0.10 0.15 1.40 1.45 0.30 0.40 — 0.20 e 22.0 22.1 20.0 20.1 16.0 16.1 b 14.0 14.1 0.65 — 0.60 0.75 1.00 — 0.10 — 7° 32/ © 2002, GSI Technology ...

Page 33

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D) BOTTOM VIEW Ø0. Ø0. Ø0.40~0.60 (165x 1.0 10.0 13±0.05 B 0.20(4x) 33/38 A1 CORNER 1.0 © 2002, GSI Technology ...

Page 34

... GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.06 6/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ...

Page 35

... GS88136BGT-333I 256K x 32 GS88132BGT-300I 256K x 32 GS88136BGT-250I 256K x 32 GS88132BGT-200I 256K x 32 GS88132BGT-150I 256K x 36 GS88136BGT-333I 256K x 36 GS88136BGT-300I 256K x 36 GS88136BGT-250I 256K x 36 GS88136BGT-200I 256K x 36 GS88136BGT-150I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS88118BT-150IT. ...

Page 36

... GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.06 6/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ...

Page 37

... GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.06 6/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ...

Page 38

... Added variation information to 165 BGA • Added Pb-free information for 165 BGA Content • Changed all Pb-free information to RoHS-compliant Content • Added status on ordering information table • Corrected 165 BGA mechanical (changed to consolidated) • Updated Truth Tables (pg. 11, 12) Content 38/38 Page;Revisions;Reason © 2002, GSI Technology ...

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