gs8662dt11bgd-500i GSI Technology, gs8662dt11bgd-500i Datasheet

gs8662dt11bgd-500i

Manufacturer Part Number

gs8662dt11bgd-500i

Description

72mb Sigmaquad-ii+tm Burst Of 4 Sram

Manufacturer

GSI Technology

Datasheet

1.GS8662DT11BGD-500I.pdf (34 pages)

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165-Bump BGA

Commercial Temp

Industrial Temp

Features

• 2.5 Clock Latency

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 4 Read and Write

• Dual-Range On-Die Termination (ODT) on Data (D), Byte

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• Data Valid Pin (QVLD) Support

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

SigmaQuad-II™ Family Overview

The GS8662DT06/11/20/38BD are built in compliance with

the SigmaQuad-II+ SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 75,497,472-bit (72Mb)

Rev: 1.00 5/2011

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Write (BW), and Clock (K, K) intputs

tKHKH

tKHQV

tKHKH

tKHQV

1.81 ns

0.29ns

-550

0.33 ns

72Mb SigmaQuad-II+

2.0 ns

-500

Parameter Synopsis (x18/x36)

Parameter Synopsis (x8/x9)

Burst of 4 SRAM

0.33 ns

2.0 ns

-500

1/34

0.37ns

2.2 ns

-450

SRAMs. The GS8662DT06/11/20/38BD SigmaQuad SRAMs

are just one element in a family of low power, low voltage

HSTL I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

Clocking and Addressing Schemes

The GS8662DT06/11/20/38BD SigmaQuad-II+ SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

Because Separate I/O SigmaQuad-II+ B4RAMs always

transfer data in four packets, A0 and A1 are internally set to 0

for the first read or write transfer, and automatically

incremented by 1 for the next transfers. Because the LSBs are

tied off internally, the address field of a SigmaQuad-II+ B4

RAM is always two address pins less than the advertised index

depth (e.g., the 4M x 18 has a 1M addressable index).

0.37 ns

2.2 ns

-450

GS8662DT20/38BD-550/500/450/400/350

0.45 ns

2.5 ns

-400

GS8662DT06/11BD-500/450/400/350

0.45 ns

2.5 ns

-400

2.86 ns

0.45 ns

-350

2.86 ns

0.45 ns

-350

550 MHz–350 MHz

1.8 V or 1.5 V I/O

1.8 V V

Related parts for gs8662dt11bgd-500i

gs8662dt11bgd-500i Summary of contents

Page 1

... Parameter Synopsis (x18/x36) -550 -500 -450 2.0 ns 2.2 ns 0.33 ns 0.37 ns Parameter Synopsis (x8/x9) -500 -450 2.0 ns 2.2 ns 0.33 ns 0.37ns 1/34 GS8662DT06/11BD-500/450/400/350 550 MHz–350 MHz TM 1 1.5 V I/O -400 -350 2.5 ns 2.86 ns 0.45 ns 0.45 ns -400 -350 2.5 ns 2.86 ns 0.45 ns 0.45 ns © 2011, GSI Technology 1 ...

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... Output — Input — Input — Output — Input — Input Active Low Output — Output — Supply 1.8 V Nominal Supply 1 1.8 V Nominal Supply — Output — Low = Low Impedance Range Input High/Float = High Impedance Range — — © 2011, GSI Technology ...

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... Nybble Write (4-bit) control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble Write Enable” and “NWx” may be substituted in all the discussion above. Rev: 1.00 5/2011 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8662DT20/38BD-550/500/450/400/350 GS8662DT06/11BD-500/450/400/350 7/34 © 2011, GSI Technology ...

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... Byte 1 D9–D17 D0–D8 Written Written Beat 2 Beat 3 /2 (i.e., to the switch point of the diff-amp receiver), which could cause DDQ 8/34 D9–D17 Don’t Care Data In Data In Data In Byte 2 Byte 1 Byte 2 D9–D17 D0–D8 D9–D17 Written Unchanged Written Beat 4 © 2011, GSI Technology ...

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... Dx stored if BWn = 0 in 4th data transfer only Write Abort No Dx stored in any of the four data transfers 10/34 GS8662DT06/11BD-500/450/400/350  K  K  n+1 n+1½ n © 2011, GSI Technology D K  n+2½ ...

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... Don’t Care Don’t Care Data In Don’t Care Data In Don’t Care Data In Don’t Care Data In Data In Data In Data In Data In Data In Data In Data In Data In D9–D17 Don’t Care Don’t Care Data In Data In © 2011, GSI Technology ...

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... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8662DT20/38BD-550/500/450/400/350 GS8662DT06/11BD-500/450/400/350 State Diagram Power-Up READ WRITE WRITE Write Address WRITE D Count = 2 D Count = D Count + 1 Always Write Address 13/34 Write NOP Load New WRITE D Count = 2 D Count = 0 Always DDR Write WRITE D Count = 1 Increment © 2011, GSI Technology ...

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... Airflow = 2 m/s 17.349 9.292 Max Units 0.05 V DDQ V + 0.3 V DDQ V – 0.1 V REF V + 0.3 V DDQ 0 DDQ Max Units 0.08 V DDQ + 0 0.5 V DDQ V – 0.2 V REF – 0 0.5 V DDQ 0.2 V © 2011, GSI Technology  JC (C°/W) 2.310 Notes — 2,3 2,3 Notes — 1,2,3 1,2,3 4,5 4,5 ...

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... GSI Technology Notes ...

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... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8662DT20/38BD-550/500/450/400/350 Read NOP CQ-Based Timing Diagram READ A1 WRITE NOOP A1 tKHIX tIVKH Q0 Q0+1 tCQLQV tQVLD tCQHQV tCQLQV tCQHQV 22/34 GS8662DT06/11BD-500/450/400/350 NOOP NOOP Q0+2 Q0+3 Q1 Q1+1 Q1+2 tCQLQX tCQHQX tCQLQX tCQHQX © 2011, GSI Technology NOOP Q1+3 tQVLD ...

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... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8662DT20/38BD-550/500/450/400/350 Read-Write CQ-Based Timing Diagram READ A2 WRITE tIVKH tKHIX tIVKH tKHIX tDVKH tKHDX D1 D1+1 D1+2 D1+3 Q0 Q0+1 tCQLQV tQVLD tCQHQV 23/34 GS8662DT06/11BD-500/450/400/350 NOOP NOOP tIVKH tKHIX tDVKH tKHDX D3 D3+1 D3+2 D3+3 Q0+2 Q0+3 Q2 Q2+1 Q2+2 tCQLQX tCQHQV tCQHQX tCQHQX tCQLQV tCQLQX © 2011, GSI Technology NOOP Q2+3 tQVLD ...

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... A0 R tKHIX tIVKH W BWx D D0 Rev: 1.00 5/2011 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8662DT20/38BD-550/500/450/400/350 Write NOP Timing Diagram Read No-op Write B Read No-op A1 tKHIX tIVKH tKHIX tIVKH tIVKH tKHDX tDVKH D1 D0+1 D0+2 D0+3 24/34 GS8662DT06/11BD-500/450/400/350 NO-OP NO-OP tKHIX D1+1 D1+2 D1+3 © 2011, GSI Technology NO-OP ...

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... Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Rev: 1.00 5/2011 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8662DT20/38BD-550/500/450/400/350 GS8662DT06/11BD-500/450/400/350 TDO should be left unconnected Description 25/34 . The JTAG output DD © 2011, GSI Technology ...

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... JTAG Tap Controller State Diagram 1 1 Select Capture DR 0 Shift Exit1 DR 0 Pause Exit2 Update 27/34 GS8662DT06/11BD-500/450/400/350 1 Select Capture IR 0 Shift Exit1 IR 0 Pause Exit2 Update © 2011, GSI Technology ...

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... If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high- Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. Rev: 1.00 5/2011 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8662DT20/38BD-550/500/450/400/350 GS8662DT06/11BD-500/450/400/350 28/34 © 2011, GSI Technology ...

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... JTAG Port Timing Diagram tTKH tTKH tTKL tTKL tTH tTS tTH tTS tTKQ tTH tTS Min Max Unit 50 — ns — — — — — ns 30/34 JTAG Port AC Test Load 50 * 30pF Distributed Test Jig Capacitance © 2011, GSI Technology ...

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... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8662DT20/38BD-550/500/450/400/350 GS8662DT06/11BD-500/450/400/350 BOTTOM VIEW A1 CORNER Ø0. Ø0. Ø0.40~0.60 (165x 1.0 10.0 13±0.05 B 0.20(4x) 31/ 1.0 © 2011, GSI Technology ...

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... GS8662DT11BD-350I GS8662DT11BGD-500 GS8662DT11BGD-450 GS8662DT11BGD-400 GS8662DT11BGD-350 GS8662DT11BGD-500I GS8662DT11BGD-450I GS8662DT11BGD-400I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8662DT38BD-400T Commercial Temperature Range Industrial Temperature Range. ...

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... Ordering Information GSI SigmaQuad-II+ SRAM 1 Org Part Number GS8662DT11BGD-350I GS8662DT20BD-550 GS8662DT20BD-500 GS8662DT20BD-450 GS8662DT20BD-400 GS8662DT20BD-350 GS8662DT20BD-550I GS8662DT20BD-500I GS8662DT20BD-450I GS8662DT20BD-400I GS8662DT20BD-350I GS8662DT20BGD-550 GS8662DT20BGD-500 GS8662DT20BGD-450 GS8662DT20BGD-400 GS8662DT20BGD-350 ...

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... RoHS-compliant 165-bump BGA SigmaQuad-II+ SRAM RoHS-compliant 165-bump BGA SigmaQuad-II+ SRAM RoHS-compliant 165-bump BGA SigmaQuad-II+ SRAM RoHS-compliant 165-bump BGA Format/Content • Creation of datasheet 34/34 Speed T J (MHz) 550 C 500 C 450 C 400 C 350 C 550 I 500 I 450 I 400 I 350 I Description of changes © 2011, GSI Technology 2 ...

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