gs820e32a GSI Technology, gs820e32a Datasheet

gs820e32a

Manufacturer Part Number

gs820e32a

Description

2mb Synchronous Burst Sram

Manufacturer

GSI Technology

Datasheet

1.GS820E32A.pdf (20 pages)

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TQFP

Commercial Temp

Industrial Temp

Features

• FT pin for user-configurable flow through or pipelined opera-

• Dual Cycle Deselect (DCD) operation

• 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipelined mode

• Byte Write (BW) and/or Global Write (GW) operation

• Common data inputs and data outputs

• Clock Control, registered, address, data, and control

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC standard 100-lead TQFP package

• RoHS-compliant 100-lead TQFP package available

Functional Description

Applications

The GS820E32A is a 2,097,152-bit high performance

synchronous SRAM with a 2-bit burst address counter.

Although of a type originally developed for Level 2 Cache

applications supporting high performance CPUs, the device

now finds application in synchronous SRAM applications,

ranging from DSP main store to networking chip set support.

Controls

Addresses, data I/Os, chip enables (E

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

Rev: 1.08 1/2009

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

tion

Through

Pipeline

3-1-1-1

2-1-1-1

Flow

2Mb Synchronous Burst SRAM

, E

), address burst

tCycle

Parameter Synopsis

155 mA

100 mA

5.5 ns

3.2 ns

9.1 ns

-180

1/20

8 ns

64K x 32

140 mA

90 mA

3.5 ns

8.5 ns

10 ns

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output Register can be controlled by

the user via the FT mode pin (Pin 14 in the TQFP). Holding

the FT mode pin low places the RAM in Flow Through mode,

causing output data to bypass the Data Output Register.

Holding FT high places the RAM in Pipelined mode,

activating the rising-edge-triggered Data Output Register.

DCD Pipelined Reads

The GS820E32A is a DCD (Dual Cycle Deselect) pipelined

synchronous SRAM. SCD (Single Cycle Deselect) versions are

also available. DCD SRAMs pipeline disable commands to the

same degree as read commands. DCD SRAMs hold the

deselect command for one full cycle and then begin turning off

their outputs just after the second rising edge of the clock.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS820E32A operates on a 3.3 V power supply and all

inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate

output power (V

from the internal circuit.

-166

6 ns

-133 (-4)

115 mA

80 mA

7.5 ns

12 ns

10 ns

4 ns

DDQ

) pins are used to decouple output noise

90 mA

65 mA

10 ns

15 ns

12 ns

5 ns

-5

GS820E32AT-180/166/133/4/5

3.3 V and 2.5 V I/O

180 MHz–133 MHz

3.3 V V

Related parts for gs820e32a

gs820e32a Summary of contents

Page 1

... ZZ signal stopping the clock (CK address burst 2 3 Memory data is retained during Sleep mode. Core and Interface Voltages The GS820E32A operates on a 3.3 V power supply and all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate output power (V from the internal circuit. Parameter Synopsis -180 -166 ...

Page 2

... Rev: 1.08 1/2009 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS820E32A 100-Pin TQFP Pinout 64K x 32 Top View 2/20 GS820E32AT-180/166/133/4 ...

Page 3

... DDQ Rev: 1.08 1/2009 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS820E32AT-180/166/133/4/5 Description Address field LSBs and Address Counter preset Inputs Address Inputs Data Input and Output pins No Connect Byte Write—Writes all enabled bytes; active low ...

Page 4

... Power Down ZZ Control Rev: 1.08 1/2009 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS820E32A Block Diagram Counter Load Register D Q Register D Q Register D Q Register D Q ...

Page 5

... ZZ H Interleaved Burst Sequence A[1: 1st address 11 00 2nd address 00 01 3rd address 01 10 4th address Note: The burst counter wraps to initial state on the 5th clock. 5/20 GS820E32AT-180/166/133/4/5 Function Linear Burst Interleaved Burst Flow Through Pipeline Active Standby A[1:0] A[1:0] A[1:0] A[1: ...

Page 6

... may be used in any combination with BW to write single or multiple bytes. D 6/20 GS820E32AT-180/166/133/4 Notes ...

Page 7

... None X H None X L None Next CR X Next CR H Next CW X Next 7/20 GS820E32AT-180/166/133/4/5 2 ADSP ADSC ADV ...

Page 8

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Simplified State Diagram X Deselect First Write Burst Write 8/20 GS820E32AT-180/166/133/4 First Read Burst Read and Write ( BW, and GW) control ...

Page 9

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Simplified State Diagram with G X Deselect First Write Burst Write 9/20 GS820E32AT-180/166/133/4 First Read Burst Read CR © 2000, GSI Technology ...

Page 10

... Symbol Min. V 3.135 DD V 2.375 DDQ V 1 –0 – with a pulse width not to exceed 20% tKC. DD 10/20 GS820E32AT-180/166/133/4/5 Value –0.5 to 4.6 –0 –0 +0.5 ( 4.6 V max.) DDQ –0 +0.5 ( 4.6 V max.) DD +/–20 +/–20 1.5 –55 to 125 –55 to 125 Typ. Max. Unit 3.3 3 ...

Page 11

... V IL Symbol Test conditions 3 OUT OUT Conditions 2 V/ns 1.25 V 1.25 V Fig. 1& 2 Output Load 1 50 * 30pF Distributed Test Jig Capacitance 11/20 GS820E32AT-180/166/133/4/5 20% tKC Typ. Max. Unit © 2000, GSI Technology ...

Page 12

... Pipeline I DD 100 105 90 Flow Through Flow Through Pipeline Flow Through 12/20 GS820E32AT-180/166/133/4/5 Min – – –  V –300 uA IL – – 2.375 V 1 3.135 V 2.4 V -166 -133 (-4) -5 –40 0 –40 0 – ...

Page 13

... GS820E32AT-180/166/133/4/5 -133(-4) -5 Unit Min Max Min Max 7.5 — 10 — ns — 4 — 1.5 — 1.5 — ns 1.5 — 1.5 — — 15 — ns — 10 — ...

Page 14

... Pipeline Mode Timing (DCD) Deselect Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont tKL tKL tKH tKH tKC tKC ADSC initiated read and E3 only sampled with ADSC tS tKQ tOHZ tH tLZ Q(A) D(B) 14/20 GS820E32AT-180/166/133/4/5 Deselect Deselect Deselected with E1 tHZ Q(C) Q(C+1) Q(C+2) Q(C+3) © 2000, GSI Technology tKQX ...

Page 15

... Flow Through Mode Timing (DCD) Deselect Write B Read C Read C+1 Read C+2 Read C+3 Read C tKL tKL tKC tKC Fixed High tS tH ADSC initiated read masks ADSP E1 masks ADSP tH tS tOHZ tLZ Q(A) D(B) Q(C) 15/20 GS820E32AT-180/166/133/4/5 Deselect tH Deselected with E1 tKQX tHZ Q(C+1) Q(C+2) Q(C+3) Q(C) © 2000, GSI Technology ...

Page 16

... Rev: 1.08 1/2009 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Sleep Mode Timing tKH tKH tKC tKC tKL tKL tZZS tZZH 16/20 GS820E32AT-180/166/133/4/5 tZZR © 2000, GSI Technology ...

Page 17

... Pull Down Drivers -20 -40 Pull Up Drivers -60 -80 -0.5 0 0.5 3. Rev: 1.08 1/2009 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS820E32A Output Driver Characteristics 1 1 Out (Pull Dow Out (Pull Up) DDQ 17/20 GS820E32AT-180/166/133/4/5 V DDQ ...

Page 18

... All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. Rev: 1.08 1/2009 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  0.10 0.15 1.40 1.45 0.30 0.40 — 0.20 e 22.0 22.1 20.0 20.1 16.0 16.1 b 14.0 14.1 0.65 — 0.60 0.75 1.00 — 0.10 7 — 18/20 GS820E32AT-180/166/133/4 © 2000, GSI Technology ...

Page 19

... GS820E32AGT-5I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS820E32AT- 166IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. ...

Page 20

... First Release of A version. Added “A” Version to 82032T/Q, 820E32TQ, and 820H32TQ Content • Complete rewrite of datasheet in order to reflect parts Content available • Reactivated 180 MHz speed bin Content • Updated format • Added Pb-Free information for TQFP Content • Updated Pb-Free to RoHS-compliant Content 20/20 GS820E32AT-180/166/133/4/5 © 2000, GSI Technology ...

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