atr0620 ATMEL Corporation, atr0620 Datasheet - Page 10

• Manufacturer Part Number: atr0620
• Description: Gps Baseband Processor - Atmel Corporation
• Manufacturer: ATMEL Corporation

4. EBI: External Bus Interface
5. AIC: Advanced Interrupt Controller
6. PIO2: Parallel I/O Controller
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ATR0620 [Preliminary]
The EBI generates the signals that control the access to the external memory or peripheral
devices. The EBI is fully programmable and can address up to 64 bytes. It has four chip selects
and a 20-bit address bus.
The 16-bit data bus can be configured to interface with 8- or 16-bit external devices. Separate
read and write control signals allow for direct memory and peripheral interfacing. The EBI sup-
ports different access protocols, allowing single clock cycle memory accesses.
The main features are:
The ATR0620 has an 8-level priority, individually maskable, vectored interrupt controller. This
feature substantially reduces the software and real time overhead in handling internal and exter-
nal interrupts.
The interrupt controller is connected to the NFIQ (fast interrupt request) and the NIRQ (standard
interrupt request) inputs of the ARM7TDMI processor. The processor’s NFIQ line can only be
asserted by the external fast interrupt request input: FIQ. The NIRQ line can be asserted by the
interrupts generated by the on-chip peripherals and the external interrupt request lines: IRQ0 to
IRQ3.
An 8-level priority encoder allows the customer to define the priority between the different NIRQ
interrupt sources. Internal sources are programmed to be level sensitive or edge triggered.
External sources can be programmed to be positive or negative edge triggered or high- or low-
level sensitive.
The ATR0620 features 32 programmable I/O lines. The I/O lines are multiplexed with on-chip
peripheral I/O signals in order to optimize the use of available package pins. The PIO2 controller
provides an internal interrupt signal to the Advanced Interrupt Controller (AIC).
• External memory mapping
• 4 active low chip select lines
• 8- or 16-bit data bus
• Byte write or byte select lines
• User interface for remap function of boot memory
• Two different read protocols
• Programmable wait state generation
• Programmable data float time
• Programmable write protection for each memory bank
4574CS–GPS–05/05