atr0620 ATMEL Corporation, atr0620 Datasheet - Page 9

• Manufacturer Part Number: atr0620
• Description: Gps Baseband Processor - Atmel Corporation
• Manufacturer: ATMEL Corporation

2. Architecture Overview
3. PDC2
4574CS–GPS–05/05
The ATR0620 architecture consists of two main buses, the Advanced System Bus (ASB) and
the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It inter-
faces the processor with the on-chip 32-bit memories and the external memories and devices by
means of the External Bus Interface (EBI). The APB is designed for accesses to on-chip periph-
erals and is optimized for low power consumption. The AMBA bridge provides an interface
between the ASB and the APB.
An on-chip Peripheral Data Controller (PDC2) transfers data between the on-chip USARTs/SPI
and the on- and off-chip memories without processor intervention. Most importantly, the PDC2
removes the processor interrupt handling overhead and significantly reduces the number of
clock cycles required for a data transfer. It can transfer up to 64 K continuous bytes without
reprogramming the starting address. As a result, the performance of the microcontroller is
increased and the power consumption reduced.
The ATR0620 peripherals are designed to be easily programmable with a minimum number of
instructions. Each peripheral has a 16-Kbyte address space allocated in the upper 3 M bytes of
the 4-GB address space. Except for the interrupt controller, the peripheral base address is the
lowest address of its memory space. The peripheral register set is composed of control, mode,
data, status and interrupt registers.
To maximize the efficiency of bit manipulation, frequently-written registers are mapped into three
memory locations. The first address is used to set the individual register bits, the second resets
the bits and the third address reads the value stored in the register. A bit can be set or reset by
writing a one to the corresponding position at the appropriate address. Writing a zero has no
effect. Individual bits can thus be modified without having to use costly read-modify-write and
complex bit-manipulation instructions.
All of the external signals of the on-chip peripherals are under the control of the parallel I/O con-
troller. The PIO2 controller can be programmed to insert an input filter on each pin or generate
an interrupt on a signal change. After reset, the user must carefully program the PIO2 controller
in order to define which peripheral signals are connected with off-chip logic.
The ARM7TDMI processor operates in little-endian mode in the ATR0620 GPS baseband. The
processor’s internal architecture and the ARM and Thumb instruction sets are described in the
ARM7TDMI data sheet. The memory map and the on-chip peripherals are described in detail in
the ATR0620 data sheet. The electrical and mechanical characteristics are also documented in
the ATR0620 data sheet.
The ARM standard In-Circuit Emulation (ICE) debug interface is supported via the ICE port of
the ATR0620.
The ATR0620 has an 8-channel PDC2 dedicated to the three on-chip USARTs and to the SPI.
One PDC2 channel is connected to the receiving channel and one to the transmitting channel of
each peripheral.
The user interface of a PDC2 channel is integrated in the memory space of each USART chan-
nel and in the memory space of the SPI. It contains a 32-bit address pointer register and a 16-bit
count register. When the programmed data is transferred, an end-of-transfer interrupt is gener-
ated by the corresponding peripheral. See the USART section and the SPI section for more
details on PDC2 operation and programming.
ATR0620 [Preliminary]
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